Eric Christopher
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4aa8024569
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For 64-bit the rest of the general regs are ok for the q constraint. Make
sure we can emit both the high and low versions of those registers.
Fixes rdar://10392864
llvm-svn: 145579
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2011-12-01 08:12:41 +00:00 |
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Nick Lewycky
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a82f7a687e
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Let the inline asm 'q' constraint match float, and on 64-bit double too.
Fixes PR9602!
llvm-svn: 134665
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2011-07-08 00:19:27 +00:00 |
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Chris Lattner
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6aa403748e
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Remove support for parsing the "type i32" syntax for defining a numbered
top level type without a specified number. This syntax isn't documented
and blocks forward progress.
llvm-svn: 133371
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2011-06-19 00:03:46 +00:00 |
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Dan Gohman
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df2896d609
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Eliminate more uses of llvm-as and llvm-dis.
llvm-svn: 81290
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2009-09-08 23:54:48 +00:00 |
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Evan Cheng
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67ccedff04
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Fix x86 inline ams 'q' constraint support. In 32-bit mode, it's just like 'Q', i.e. EAX, EDX, ECX, EBX. In 64-bit mode, it just means all the i64r registers. Yeah, that makes sense.
llvm-svn: 76248
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2009-07-17 22:13:25 +00:00 |
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