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76 Commits

Author SHA1 Message Date
Chris Lattner
ed9a2f6371 in ppc64-mode, don't allocate the 32-bit version of r13 either. 
llvm-svn: 31884
 2006-11-20 20:48:05 +00:00
Chris Lattner
ad5f088196 r13 is the thread pointer on darwin/ppc64, don't allocate it. 
llvm-svn: 31882
 2006-11-20 19:33:51 +00:00
Jim Laskey
8aac7dc0ee This is a general clean up of the PowerPC ABI. Address several problems and 
bugs including making sure that the TOS links back to the previous frame,
that the maximum call frame size is not included twice when using frame
pointers, no longer growing the frame on calls, double storing of SP and
a cleaner/faster dynamic alloca.

llvm-svn: 31792
 2006-11-16 22:43:37 +00:00
Chris Lattner
dc48b6a77c Rework PPC64 calls. Now we have a LR8/CTR8 register which the PPC64 calls 
clobber.  This allows LR8 to be save/restored correctly as a 64-bit quantity,
instead of handling it as a 32-bit quantity.  This unbreaks ppc64 codegen when
the code is actually located above the 4G boundary.

llvm-svn: 31734
 2006-11-14 18:44:47 +00:00
Chris Lattner
db290f7479 Constify some methods. Patch provided by Anton Vayvod, thanks! 
llvm-svn: 29756
 2006-08-17 22:00:08 +00:00
Chris Lattner
126464b577 Remove the -darwin and -aix llc options, inferring darwinism and aixism from 
the target triple & subtarget info.  woo.

llvm-svn: 28835
 2006-06-16 18:50:48 +00:00
Chris Lattner
20affbd29a Revert Nate's CR patch from last night, which caused many regressions (e.g. fhourstones). 
Loading and storing off R0 isn't what we wanted.  Also, taking some CR's out of
CRRC seems to cause failures as well.  Further investigation is required.

llvm-svn: 28097
 2006-05-04 16:56:45 +00:00
Nate Begeman
d7b4d2a743 Since we don't handle callee-save CRs right yet, don't allocate them. Also 
don't step on R11 in the middle of a function when saving and restoring CRs

llvm-svn: 28058
 2006-05-02 17:37:31 +00:00
Chris Lattner
a717d4f53b Prefer to allocate V2-V5 before V0,V1. This lets us generate code like this: 
vspltisw v2, -12
        vrlw v2, v2, v2

instead of:

        vspltisw v0, -12
        vrlw v2, v0, v0

when a function is returning a value.

llvm-svn: 27771
 2006-04-17 21:19:12 +00:00
Chris Lattner
7f5fba9c67 add all supported formats to the vector register file 
llvm-svn: 27115
 2006-03-25 07:36:56 +00:00
Jim Laskey
1716e53341 Add dwarf register numbering to register data. 
llvm-svn: 27081
 2006-03-24 21:15:58 +00:00
Chris Lattner
65e6e12dca Claim to have v16i8 for perm masks 
llvm-svn: 26886
 2006-03-20 01:53:02 +00:00
Chris Lattner
d0505331d2 For functions that use vector registers, save VRSAVE, mark used 
registers, and update it on entry to each function, then restore it on exit.

This compiles:

void func(vfloat *a, vfloat *b, vfloat *c) {
        *a = *b * *c + *c;
}

to this:

_func:
        mfspr r2, 256
        oris r6, r2, 49152
        mtspr 256, r6
        lvx v0, 0, r5
        lvx v1, 0, r4
        vmaddfp v0, v1, v0, v0
        stvx v0, 0, r3
        mtspr 256, r2
        blr

GCC produces this (which has additional stack accesses):

_func:
        mfspr r0,256
        stw r0,-4(r1)
        oris r0,r0,0xc000
        mtspr 256,r0
        lvx v0,0,r5
        lvx v1,0,r4
        lwz r12,-4(r1)
        vmaddfp v0,v0,v1,v0
        stvx v0,0,r3
        mtspr 256,r12
        blr

llvm-svn: 26733
 2006-03-13 21:52:10 +00:00
Evan Cheng
e458553c73 Bye bye HACKTROCITY. 
llvm-svn: 24935
 2005-12-22 02:26:21 +00:00
Nate Begeman
a114534620 Pattern-match return. Includes gross hack! 
llvm-svn: 24874
 2005-12-20 00:26:01 +00:00
Nate Begeman
69da94a1b9 Add a second vector type to the VRRC register class, and fix some patterns 
so that tablegen can infer all types.

llvm-svn: 24746
 2005-12-16 09:19:13 +00:00
Nate Begeman
811a41a87c Support multiple ValueTypes per RegisterClass, needed for upcoming vector 
work.  This change has no effect on generated code.

llvm-svn: 24563
 2005-12-01 04:51:06 +00:00
Nate Begeman
5de40afc43 Cosmetic change, better reflects actual values 
llvm-svn: 24562
 2005-12-01 04:48:26 +00:00
Nate Begeman
a1c2df2471 Add the majority of the vector machien value types we expect to support, 
and make a few changes to the legalization machinery to support more than
16 types.

llvm-svn: 24511
 2005-11-29 05:45:29 +00:00
Chris Lattner
2e375c1847 don't say this is i128, because it isn't yet. Hopefully nate will change 
this to be something sane, but in the mean time it is unused, so safe to
make something bogus.

llvm-svn: 24504
 2005-11-29 00:41:40 +00:00
Nate Begeman
84cac055ad Small tweaks noticed while on the plane. 
llvm-svn: 24492
 2005-11-26 22:39:34 +00:00
Nate Begeman
687456dd7a Some first bits of AltiVec stuff: Instruction Formats, Encodings, and 
Registers.  Apologies to Jim if the scheduling info so far isn't accurate.

There's a few more things like VRsave support that need to be finished up
in my local tree before I can commit code that Does The Right Thing for
turning 4 x float into the various altivec packed float instructions.

llvm-svn: 24489
 2005-11-23 05:29:52 +00:00
Chris Lattner
6416c5627d apply some tblgen majik to simplify the X register definitions 
llvm-svn: 23805
 2005-10-19 00:17:55 +00:00
Nate Begeman
722531ea21 Make a new reg class for 64 bit regs that aliases the 32 bit regs. This 
will have to tide us over until we get real subreg support, but it prevents
the PrologEpilogInserter from spilling 8 byte GPRs on a G4 processor.

Add some initial support for TRUNCATE and ANY_EXTEND, but they don't
currently work due to issues with ScheduleDAG.  Something wll have to be
figured out.

llvm-svn: 23803
 2005-10-19 00:05:37 +00:00
Nate Begeman
b0e319a7c7 First bits of 64 bit PowerPC stuff, currently disabled. A lot of this is 
purely mechanical.

llvm-svn: 23778
 2005-10-18 00:28:58 +00:00
Chris Lattner
11127fcf98 Rename PowerPC*.td -> PPC*.td 
llvm-svn: 23740
 2005-10-14 23:40:39 +00:00