1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-22 18:54:02 +01:00
Commit Graph

218933 Commits

Author SHA1 Message Date
Tianqing Wang
5f5c9808cd [X86] Update MachineLoopInfo in CMOV conversion.
If a CMOV is in a loop and is converted to branches, CMOV conversion wouldn't
add newly created basic blocks to loop info. Since the candidates is collected
based on loops, instructions in these basic blocks will be ignored.

Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D104623
2021-07-21 10:53:46 +08:00
Ben Shi
6b99631a69 [RISCV][test] Add tests for mul optimization in the zba extension with SH*ADD
These tests will show the following optimization by future patches.

(mul x, 11) -> (SH1ADD (SH2ADD x, x), x)
(mul x, 19) -> (SH1ADD (SH3ADD x, x), x)
(mul x, 13) -> (SH2ADD (SH1ADD x, x), x)
(mul x, 21) -> (SH2ADD (SH2ADD x, x), x)
(mul x, 37) -> (SH2ADD (SH3ADD x, x), x)
(mul x, 25) -> (SH3ADD (SH1ADD x, x), x)
(mul x, 41) -> (SH3ADD (SH2ADD x, x), x)
(mul x, 73) -> (SH3ADD (SH3ADD x, x), x)

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D106031
2021-07-21 10:16:56 +08:00
Vitaly Buka
9d59adc48f [NFC][hwasan] Remove "pragma GCC poison"
With ifdefs they make code less readable.
2021-07-20 19:10:05 -07:00
Vitaly Buka
91284a6419 [NFC][hwasan] Simplify expression 2021-07-20 19:10:05 -07:00
Alexander Yermolovich
7c0f448127 [DWP] Fix for Refactoring llvm-dwp in to a library
Fix build for https://reviews.llvm.org/D106198 when -DBUILD_SHARED_LIBS=ON. Test Plan:

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D106414
2021-07-20 18:17:24 -07:00
Jon Roelofs
5f81593d96 [MachineVerifier] Diagnose invalid INSERT_SUBREGs
Differential revision: https://reviews.llvm.org/D105953
2021-07-20 17:32:29 -07:00
LLVM GN Syncbot
2c7e558308 [gn build] Port 403e67d34d03 2021-07-21 00:19:59 +00:00
Alexander Yermolovich
ba558b5d3e [DWP] Refactoring llvm-dwp in to a library.
This is a step1, mechanical refactor, of moving the bulk of llvm-dwp functionality in to a library. This should allow other tools, like BOLT, to re-use some of the llvm-dwp functionality.

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D106198
2021-07-20 17:19:26 -07:00
Jon Roelofs
22051ac0d6 [GlobalISel] Tail call memcpy/memmove/memset even in the presence of copies
Differentail revision: https://reviews.llvm.org/D105382
2021-07-20 17:04:33 -07:00
Jon Roelofs
98d4971f24 [GlobalISel] Mark memcpy/memmove/memset as thisreturn
https://clang.godbolt.org/z/9az64j8W6

rdar://77466123

Differential revision: https://reviews.llvm.org/D105370
2021-07-20 17:04:33 -07:00
Lang Hames
53129328a6 Revert "[ORC][ORC-RT] Add initial native-TLV support to MachOPlatform."
Reverts commit fe1fa43f16beac1506a2e73a9f7b3c81179744eb while I investigate
failures on Linux.
2021-07-21 09:22:55 +10:00
Lang Hames
ad6b1171f3 [ORC][ORC-RT] Add initial native-TLV support to MachOPlatform.
Adds code to LLVM (MachOPlatform) and the ORC runtime to support native MachO
thread local variables. Adding new TLVs to a JITDylib at runtime is supported.

On the LLVM side MachOPlatform is updated to:

1. Identify thread local variables in the LinkGraph and lower them to GOT
accesses to data in the __thread_data or __thread_bss sections.

2. Merge and report the address range of __thread_data and thread_bss sections
to the runtime.

On the ORC runtime a MachOTLVManager class introduced which records the address
range of thread data/bss sections, and creates thread-local instances from the
initial data on demand. An orc-runtime specific tlv_get_addr implementation is
included which saves all register state then calls the MachOTLVManager to get
the address of the requested variable for the current thread.
2021-07-21 09:10:10 +10:00
Lang Hames
b5215e41fc [JITLink][MachO] Detect MachO::S_THREAD_LOCAL_ZEROFILL sections as zero-fill.
This will be used in upcoming MachO native TLV support patches to LLVM and
the ORC runtime.
2021-07-21 09:10:10 +10:00
Lang Hames
255fc69d3a [JITLink] Add support for moving blocks and symbols between sections.
LinkGraph::transferBlock can be used to move a block and all associated symbols
from one section to another.

LinkGraph::mergeSections moves all blocks and sections from a source section to
a destination section.
2021-07-21 09:10:09 +10:00
Albion Fung
d88c540901 [PowerPC] Implemented mtmsr, mfspr, mtspr Builtins
Implemented builtins for mtmsr, mfspr, mtspr on PowerPC;
the patch is intended for XL Compatibility.

Differential revision: https://reviews.llvm.org/D106130
2021-07-20 17:51:00 -05:00
Aditya Nandakumar
3b84dfd020 [NFC][AssemblyWriter] Allow AssemblyWriter::printBasicBlock() to print blocks that don't have parents.
Remove the assert in AssemblyWriter::printBasicBlock() and
in BasicBlock::isEntryBlock() that require blocks to have parents.
Instead, have BasicBlock::isEntryBlock() return false for unattached
blocks. This allows us to call these functions for blocks that are
not yet added to a module which is a useful debugging capability.

Committing for xiaoqing_wu

https://reviews.llvm.org/D106127k
2021-07-20 15:46:31 -07:00
Jon Roelofs
efa9e99cf1 [tests] Move new tests into the PowerPC folder
That way they get marked as UNSUPPORTED by LIT when the ppc backend has not
been built.
2021-07-20 15:37:56 -07:00
Jon Roelofs
ff40770cd1 [AArch64][GlobalISel] Legalize ctpop for v2s64, v2s32, v4s32, v4s16, v8s16
https://llvm.godbolt.org/z/nTTK6M5qe

Differential revision: https://reviews.llvm.org/D106388
2021-07-20 15:37:56 -07:00
Sanjay Patel
cc2611c224 [ConstantFolding] avoid crashing on a fake math library call
https://llvm.org/PR50960
2021-07-20 18:25:21 -04:00
LLVM GN Syncbot
a36faebe1f [gn build] Port 808bbc2c4702 2021-07-20 21:53:24 +00:00
Alex Lorenz
e6cc4def5d [clang][darwin] Add support for macOS -> Mac Catalyst
version remapping to the Darwin SDK Info

Differential Revision: https://reviews.llvm.org/D105958
2021-07-20 14:25:33 -07:00
Roman Lebedev
8dc35a0179 [NFC][VectorCombine] Add tests for widening of partial vector load 2021-07-21 00:24:47 +03:00
Eli Friedman
b6a5af5997 [AArch64] Add tests for 128-bit atomic loads with casp available.
We currently don't use casp; maybe we should?
2021-07-20 14:02:44 -07:00
Sami Tolvanen
515d9b0199 Revert "ThinLTO: Fix inline assembly references to static functions with CFI"
This reverts commit 700d07f8ce6f2879610fd6b6968b05c6f17bb915.

Reverting due to a ThinLTO+CFI breakage on -msvc targets.
2021-07-20 13:59:46 -07:00
LLVM GN Syncbot
e479de9d16 [gn build] Port 05a6d74c4845 2021-07-20 20:51:01 +00:00
Albion Fung
63ce4846c7 [PowerPC] Store, load, move from and to registers related builtins
This patch implements store, load, move from and to registers related
builtins, as well as the builtin for stfiw. The patch aims to provide
feature parady with xlC on AIX.

Differential revision: https://reviews.llvm.org/D105946
2021-07-20 15:46:14 -05:00
Sterling Augustine
c4088202b5 Consolidate string types into ptr and length representations.
After rGbbbc4f110e35ac709b943efaa1c4c99ec073da30, we can move
any string type that has convenient pointer and length fields
into the PtrAndLengthKind, reducing the amount of code.

Differential Revision: https://reviews.llvm.org/D106381
2021-07-20 13:29:57 -07:00
Jessica Paquette
16d5479ea5 [AArch64][GlobalISel] Select llvm.aarch64.neon.st2 intrinsics
Add manual selection code similar to the code in AArch64ISelDAGToDAG, and add
`createTuple` helpers similar to the code there as well.

This accounted for around 111 fallbacks while building clang for AArch64 with
GlobalISel.

This also should make it easy to add selection code for other store
intrinsics.

As a minor cleanup, this uses `createQTuple` in the other place where we use
REG_SEQUENCE.

Differential Revision: https://reviews.llvm.org/D106332
2021-07-20 13:23:46 -07:00
Eli Friedman
a773ea23aa [AArch64] Use the CMP_SWAP_128 variants added in 843c6140.
Accidentally forgot to flip the opcode... and I didn't notice because it
was working fine for the GlobalISel.
2021-07-20 13:23:27 -07:00
Fangrui Song
2174d3b961 [LTO] Add SelectionKind to IRSymtab and use it in ld.lld/LLVMgold
In PGO, a C++ external linkage function `foo` has a private counter
`__profc_foo` and a private `__profd_foo` in a `comdat nodeduplicate`.

A `__attribute__((weak))` function `foo` has a weak hidden counter `__profc_foo`
and a private `__profd_foo` in a `comdat nodeduplicate`.

In `ld.lld a.o b.o`, say a.o defines an external linkage `foo` and b.o
defines a weak `foo`. Currently we treat `comdat nodeduplicate` as `comdat any`,
ld.lld will incorrectly consider `b.o:__profc_foo` non-prevailing.  In the worst
case when `b.o:__profd_foo` is retained and `b.o:__profc_foo` isn't, there will
be dangling reference causing an `undefined hidden symbol` error.

Add SelectionKind to `Comdat` in IRSymtab and let linkers ignore nodeduplicate comdat.

Differential Revision: https://reviews.llvm.org/D106228
2021-07-20 13:22:00 -07:00
Fangrui Song
afd2d1339a [AArch64] Delete unused Opcode after D106039 2021-07-20 12:51:44 -07:00
Fangrui Song
dd6e19a41c [IR] Rename comdat noduplicates to comdat nodeduplicate
In the textual format, `noduplicates` means no COMDAT/section group
deduplication is performed. Therefore, if both sets of sections are retained, and
they happen to define strong external symbols with the same names,
there will be a duplicate definition linker error.

In PE/COFF, the selection kind lowers to `IMAGE_COMDAT_SELECT_NODUPLICATES`.
The name describes the corollary instead of the immediate semantics.  The name
can cause confusion to other binary formats (ELF, wasm) which have implemented/
want to implement the "no deduplication" selection kind. Rename it to be clearer.

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D106319
2021-07-20 12:47:10 -07:00
Shilei Tian
0d5ca9b780 [OpenMP][deviceRTLs] Update return type of function __kmpc_parallel_level
In `deviceRTLs`, the parallel level is stored in a shared variable of type `uint8_t`.
`__kmpc_parallel_level` currently returns a 16-bit interger. This patch first
changes the return type of the function to `uint8_t`, same as the shared variable,
and then corrects function type which was updated in D105955.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D106384
2021-07-20 15:45:43 -04:00
Eli Friedman
91da841387 [AArch64] Fix i128 cmpxchg using ldxp/stxp.
Basically two parts to this fix:

1. Stop using AtomicExpand to expand cmpxchg i128
2. Fix AArch64ExpandPseudoInsts to use a correct expansion.

From ARM architecture reference:

To atomically load two 64-bit quantities, perform a Load-Exclusive
pair/Store-Exclusive pair sequence of reading and writing the same value
for which the Store-Exclusive pair succeeds, and use the read values
from the Load-Exclusive pair.

Fixes https://bugs.llvm.org/show_bug.cgi?id=51102

Differential Revision: https://reviews.llvm.org/D106039
2021-07-20 12:38:12 -07:00
Nikita Popov
8c4fc78279 [AttrBuilder] Assert correct attribute kind
Make sure that addAttribute() is only used with simple enum
attributes. Integer and type attributes need to provide an
additional value/type.
2021-07-20 21:16:23 +02:00
Albion Fung
908ee30339 [PowerPC] Extra test case for LDARX
An extra test case added for the builtin __LDARX.

Differential revision: https://reviews.llvm.org/D105926
2021-07-20 14:15:15 -05:00
Nikita Popov
db5e50afb3 [BitcodeReader] Handle type attributes more explicitly (NFCI)
For attributes in legacy bitcode that are now typed, explicitly
create a type attribute with nullptr type, the same as we do
for the attribute group representation. This is so we can assert
use of the correct constructor in the future.
2021-07-20 21:08:06 +02:00
Nikita Popov
aa40b02846 [Orc] Fix sret/byval attributes in test (NFC)
This was placing sret/byval attributes without type argument on
non-pointer arguments. Make this valid IR by using pointer
arguments and passing the corresponding attribute type argument.
2021-07-20 20:47:15 +02:00
Graham Yiu
23d5a10c04 [NFC] Update code owners file
- Replace Pete with Mark as owner of ARC backend
- Re-order Philip to be sorted by first name
2021-07-20 11:29:10 -07:00
Nikita Popov
aff28b4fbb [ThinTLOBitcodeWriter] Fix unused variable warning (NFC) 2021-07-20 20:19:47 +02:00
Nikita Popov
168546a427 [Verifier] Check byval/etc type when comparing ABI attributes
For musttail calls, ABI attributes between the function and the
musttail call must match. The current check discards the type of
type attributes like byval, which means that it will consider
byval(i32) and byval(i64) (or similar) as compatible.

I assume this is a leftover from before these attributes had a
type argument. Ran into this while trying to tighten an assertion
in AttrBuilder.

Differential Revision: https://reviews.llvm.org/D105841
2021-07-20 20:19:47 +02:00
Victor Huang
f281101580 [PowerPC] Add PowerPC cmpb builtin and emit target indepedent code for XL compatibility
This patch is in a series of patches to provide builtins for compatibility
with the XL compiler. This patch add the builtin and emit target independent
code for __cmpb.

Reviewed By: nemanjai, #powerpc

Differential revision: https://reviews.llvm.org/D105194
2021-07-20 13:06:22 -05:00
Jacob Hegna
a61a8e3a6d Fix Threshold overwrite bug in the Oz inlining model features.
Differential Revision: https://reviews.llvm.org/D106336
2021-07-20 18:05:06 +00:00
Zequan Wu
33cf5f7023 [Utils] Add -compilation-dir flag to prepare-code-coverage-artifact.py
Differential Revision: https://reviews.llvm.org/D106314
2021-07-20 10:55:49 -07:00
Nikita Popov
8eac42b1cf [Inline] Fix noalias addition on simplified instructions (PR50589)
When adding noalias/alias.scope metadata, we analyze the instructions
of the original callee, and then place metadata on the corresponding
inlined instructions in the caller as provided by VMap. However, this
assumes that this actually a clone of the instruction, rather than
the result of simplification. If simplification occurred, the
instruction that VMap points to may not have any relationship as far
as ModRef behavior is concerned.

Fix this by tracking simplified instructions during cloning and then
only processing instructions that have not been simplified. This is
done with an additional map form original to cloned instruction,
into which we only insert if no simplification is performed. The
mapping in VMap can then be compared to this map. If they're the
same, the instruction hasn't been simplified. (I originally wanted
to only track a set of simplified instructions, but that wouldn't
work if the instruction only gets simplified afterwards, e.g. based
on rewritten phis.)

Fixes https://bugs.llvm.org/show_bug.cgi?id=50589.

Differential Revision: https://reviews.llvm.org/D106242
2021-07-20 19:52:41 +02:00
Sami Tolvanen
8bbf0d9c0e ThinLTO: Fix inline assembly references to static functions with CFI
Create an internal alias with the original name for static functions
that are renamed in promoteInternals to avoid breaking inline
assembly references to them. This version uses module inline assembly
to avoid issues with LowerTypeTestsModule.

Relands commmit 8e3b5cb39eef462943ed7556469604ce25c07a1d with arch
specific tests fixed.

Link: https://github.com/ClangBuiltLinux/linux/issues/1354

Reviewed By: nickdesaulniers, pcc

Differential Revision: https://reviews.llvm.org/D104058
2021-07-20 10:30:02 -07:00
Arthur Eubanks
d577e2748f [NewPM] Print pre-transformation IR name in --print-after-all
Sometimes a transformation can change the name of some IR (e.g. an SCC
with functions added/removed). This can be confusing when debug logging
doesn't match the post-transformation name. The specific example I came
across was that --print-after-all said the inliner was working on an SCC
that only contained one function, but calls in multiple functions were
getting inlined. After all inlining, the current SCC only contained one
function.

Piggyback off of the existing logic to handle invalidated IR +
--print-module-scope. Simply always store the IR description and use
that.

Reviewed By: jamieschmeiser

Differential Revision: https://reviews.llvm.org/D106290
2021-07-20 10:20:10 -07:00
Giorgis Georgakoudis
43d4e670a4 [OpenMP] Set RequiresFullRuntime false in SPMDization
SPMDization in D102307 does not change the RequiresFullRuntime argument of kmpc_target_init/deinit calls. However, the constraints of SPMDization detection for converting a target region to SPMD mode should guarantee that the region does not require full runtime support. Hence, this patch sets RequiresFullRuntime to false for improved execution performance.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D105556
2021-07-20 09:54:51 -07:00
Fangrui Song
dcddd93e08 [test] Avoid llvm-symbolizer/llvm-addr2line one-dash long options 2021-07-20 09:34:35 -07:00
Shimin Cui
74b9048a41 This patch extends the OptimizeGlobalAddressOfMalloc to handle the null check of global pointer variables. It is disabled with https://reviews.llvm.org/rGb7cd291c1542aee12c9e9fde6c411314a163a8ea. This PR is to reenable it while fixing the original problem reported. The fix is to set the store value correctly when creating store for the new created global init bool symbol.
Reviewed By: efriedma

Differential Revision:  https://reviews.llvm.org/D102711
2021-07-20 12:27:26 -04:00