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2 Commits

Author SHA1 Message Date
Geoff Berry
b227d8b168 [AArch64] Improved bitfield instruction selection. 
Summary:
For bitfield insert OR matching, check both operands for larger pattern
first before checking for smaller pattern.

Add pattern for unsigned bitfield insert-in-zero done with SHL+AND.

Resolves PR21631.

Reviewers: jmolloy, t.p.northover

Subscribers: aemerson, rengolin, llvm-commits, mcrosier

Differential Revision: http://reviews.llvm.org/D12908

llvm-svn: 248006
 2015-09-18 17:11:53 +00:00
Arnaud A. de Grandmaison
90c89b61da [AArch64] Select SBFIZ or UBFIZ instead of left + right shifts 
And rename LSB to Immr / MSB to Imms to match the ARM ARM terminology.

llvm-svn: 241803
 2015-07-09 14:33:38 +00:00