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Commit Graph

22510 Commits

Author SHA1 Message Date
Chad Rosier
c928e82253 Revert r167620; this can be implemented using an existing CL option.
llvm-svn: 167622
2012-11-09 18:25:27 +00:00
Chad Rosier
2962c226a7 Add support for -mstrict-align compiler option for ARM targets.
rdar://12340498

llvm-svn: 167620
2012-11-09 17:29:38 +00:00
Nadav Rotem
41e4da88d8 indent
llvm-svn: 167607
2012-11-09 07:02:24 +00:00
Amara Emerson
f7a46cedbc Recommit modified r167540.
Improve ARM build attribute emission for architectures types.
This also changes the default architecture emitted for a generic CPU to "v7".

llvm-svn: 167574
2012-11-08 09:51:45 +00:00
Michael Liao
59114df23b Add support of RTM from TSX extension
- Add RTM code generation support throught 3 X86 intrinsics:
  xbegin()/xend() to start/end a transaction region, and xabort() to abort a
  tranaction region

llvm-svn: 167573
2012-11-08 07:28:54 +00:00
Akira Hatanaka
b8f5a8ab0b [mips] Custom-lower ISD::FRAME_TO_ARGS_OFFSET node.
Patch by Sasa Stankovic.

llvm-svn: 167548
2012-11-07 19:10:58 +00:00
Akira Hatanaka
381d412e60 Delete MipsFunctionInfo::NextStackOffset. No functionality change intended.
llvm-svn: 167546
2012-11-07 19:04:26 +00:00
Amara Emerson
8c6795b9fc Revert r167540 until regression tests are updated.
llvm-svn: 167545
2012-11-07 18:57:14 +00:00
Amara Emerson
44340f40d7 Improve ARM build attribute emission for architectures types.
This also changes the default architecture emitted for a generic CPU to "v7".

llvm-svn: 167540
2012-11-07 18:01:03 +00:00
Chad Rosier
ec9f0f3363 [arm fast-isel] Appease the machine verifier by using the proper register
classes.  For my test case the number of errors drop from 356 to 21.
Part of rdar://12594152

llvm-svn: 167508
2012-11-07 00:13:01 +00:00
Jakub Staszak
473b6f7d13 Simplify code. No functionality change.
llvm-svn: 167505
2012-11-06 23:52:19 +00:00
Nadav Rotem
37812539c2 Make the helper functions static. No functional change.
llvm-svn: 167501
2012-11-06 23:36:00 +00:00
Chad Rosier
37889b06ad Mark the Int_eh_sjlj_dispatchsetup pseudo instruction as clobbering all
registers.  Previously, the register we being marked as implicitly defined, but
not killed.  In some cases this would cause the register scavenger to spill a
dead register.

Also, use an empty register mask to simplify the logic and to reduce the memory
footprint.
rdar://12592448

llvm-svn: 167499
2012-11-06 23:05:24 +00:00
Nadav Rotem
dce9a7a599 CostModel: add another known vector trunc optimization.
llvm-svn: 167488
2012-11-06 21:17:17 +00:00
Nadav Rotem
2fb5dc3a15 Cost Model: add tables for some avx type-conversion hacks.
llvm-svn: 167480
2012-11-06 19:33:53 +00:00
Michael Liao
58efdb2214 Remove tailing whitespaces
llvm-svn: 167445
2012-11-06 08:06:35 +00:00
Andrew Trick
76ebc86f9a ScheduleDAG interface. Added OrderKind to distinguish nonregister dependencies.
This is in preparation for adding "weak" DAG edges, but generally
simplifies the design.

llvm-svn: 167435
2012-11-06 03:13:46 +00:00
Nadav Rotem
514a3cb69c Refactor the getTypeLegalizationCost interface. No functionality change.
llvm-svn: 167422
2012-11-05 23:57:45 +00:00
Nadav Rotem
890d7c7f8e CostModel: Add tables for the common x86 compares.
llvm-svn: 167421
2012-11-05 23:48:20 +00:00
Nadav Rotem
8ddfd47801 Code Model: Improve the accuracy of the zext/sext/trunc vector cost estimation.
llvm-svn: 167412
2012-11-05 22:20:53 +00:00
Richard Smith
0befa1c4e0 Suppress signed/unsigned comparison warning.
llvm-svn: 167410
2012-11-05 22:01:44 +00:00
Nadav Rotem
04d64771f6 Cost Model: Normalize the insert/extract index when splitting types
llvm-svn: 167402
2012-11-05 21:12:13 +00:00
Nadav Rotem
a504aa057e Cost Model: teach the cost model about expanding integers.
llvm-svn: 167401
2012-11-05 21:11:10 +00:00
Ulrich Weigand
5e496676d0 On PowerPC64, integer return values (as well as arguments) are supposed
to be extended to a full register.   This is modeled in the IR by marking
the return value (or argument) with a signext or zeroext attribute.

However, while these attributes are respected for function arguments,
they are currently ignored for function return values by the PowerPC
back-end.  This patch updates PPCCallingConv.td to ask for the promotion
to i64, and fixes LowerReturn and LowerCallResult to implement it.

The new test case verifies that both arguments and return values are
properly extended when passing them; and also that the optimizers
understand incoming argument and return values are in fact guaranteed
by the ABI to be extended.

The patch caused a spurious breakage in CodeGen/PowerPC/coalesce-ext.ll,
since the test case used a "ret" instruction to create a use of an i32
value at the end of the function (to set up data flow as required for
what the test is intended to test).  Since there's now an implicit
promotion to i64, that data flow no longer works as expected.  To fix
this, this patch now adds an extra "add" to ensure we have an appropriate
use of the i32 value.

llvm-svn: 167396
2012-11-05 19:39:45 +00:00
Nadav Rotem
4def3aace5 Implement the cost of abnormal x86 instruction lowering as a table.
llvm-svn: 167395
2012-11-05 19:32:46 +00:00
Hal Finkel
a82b79fc22 Add support for the PowerPC-specific inline asm Z constraint and y modifier.
The Z constraint specifies an r+r memory address, and the y modifier expands
to the "r, r" in the asm string. For this initial implementation, the base
register is forced to r0 (which has the special meaning of 0 for r+r addressing
on PowerPC) and the full address is taken in the second register. In the
future, this should be improved.

llvm-svn: 167388
2012-11-05 18:18:42 +00:00
Adhemerval Zanella
382ede5fd4 [PATCH] PowerPC: Expand load extend vector operations
This patch expands the SEXTLOAD, ZEXTLOAD, and EXTLOAD operations for
vector types when altivec is enabled.

llvm-svn: 167386
2012-11-05 17:15:56 +00:00
Craig Topper
6061cb08cf Remove alignments from folding tables for scalar FMA4 instructions.
llvm-svn: 167366
2012-11-04 04:40:08 +00:00
Akira Hatanaka
1bfa522bfe [mips] Set flag neverHasSideEffects flag on floating point conversion
instructions.

llvm-svn: 167348
2012-11-03 00:53:12 +00:00
Nadav Rotem
c9bbabd5e9 X86 CostModel: Add support for a some of the common arithmetic instructions for SSE4, AVX and AVX2.
llvm-svn: 167347
2012-11-03 00:39:56 +00:00
Akira Hatanaka
61434a3632 [mips] Set flag isAsCheapAsAMove flag on instruction LUi.
llvm-svn: 167345
2012-11-03 00:26:02 +00:00
Akira Hatanaka
06b2c52edc [mips] Stop reserving register AT and use register scavenger when a scratch
register is needed.

llvm-svn: 167341
2012-11-03 00:05:43 +00:00
Akira Hatanaka
a639da5486 [mips] Do not reserve all 64-bit registers, but only the ones which need to be
reserved. Without this fix, RegScavenger::getRegsAvailable incorrectly
returns an empty set of integer registers.

llvm-svn: 167335
2012-11-02 23:36:01 +00:00
Nadav Rotem
6f0c234b7f Add a stub for the x86 cost model impl. Implement a basic cost rule for inserting/extracting from XMM registers.
llvm-svn: 167333
2012-11-02 23:27:16 +00:00
Nadav Rotem
60d5bfa82e Scalar Bitcasts and Truncs are usually free
llvm-svn: 167323
2012-11-02 21:47:47 +00:00
Quentin Colombet
522698f693 Vext Lowering was missing opportunities
llvm-svn: 167318
2012-11-02 21:32:17 +00:00
Akira Hatanaka
25aba90c6b [mips] Use register number instead of name to print register $AT.
llvm-svn: 167315
2012-11-02 21:26:03 +00:00
Akira Hatanaka
6c6c861981 [mips] Add function MipsFrameLowering::estimateStackSize.
This function estimates stack size and will be called before
PrologEpilogInserter scans the callee-saved registers.

llvm-svn: 167313
2012-11-02 21:10:22 +00:00
Akira Hatanaka
321046d38a [mips] Add member field MipsFunctionInfo::IncomingArgSize which holds the size
of the incoming argument area.

llvm-svn: 167312
2012-11-02 21:03:58 +00:00
Akira Hatanaka
ba57d98a50 [mips] Delete MipsFunctionInfo::EmitNOAT. Unconditionally print directive
"set .noat" so that the assembler doesn't issue warnings when register $AT is
used.

llvm-svn: 167310
2012-11-02 20:56:25 +00:00
Pranav Bhandarkar
c796c7d713 Use the relationship models infrastructure to add two relations - getPredOpcode
and getPredNewOpcode. The first relates non predicated instructions with their
predicated forms and the second relates predicated instructions with their
predicate-new forms.

Patch by Jyotsna Verma!

llvm-svn: 167243
2012-11-01 19:13:23 +00:00
Chandler Carruth
0a6b99ee2b Revert the majority of the next patch in the address space series:
r165941: Resubmit the changes to llvm core to update the functions to
         support different pointer sizes on a per address space basis.

Despite this commit log, this change primarily changed stuff outside of
VMCore, and those changes do not carry any tests for correctness (or
even plausibility), and we have consistently found questionable or flat
out incorrect cases in these changes. Most of them are probably correct,
but we need to devise a system that makes it more clear when we have
handled the address space concerns correctly, and ideally each pass that
gets updated would receive an accompanying test case that exercises that
pass specificaly w.r.t. alternate address spaces.

However, from this commit, I have retained the new C API entry points.
Those were an orthogonal change that probably should have been split
apart, but they seem entirely good.

In several places the changes were very obvious cleanups with no actual
multiple address space code added; these I have not reverted when
I spotted them.

In a few other places there were merge conflicts due to a cleaner
solution being implemented later, often not using address spaces at all.
In those cases, I've preserved the new code which isn't address space
dependent.

This is part of my ongoing effort to clean out the partial address space
code which carries high risk and low test coverage, and not likely to be
finished before the 3.2 release looms closer. Duncan and I would both
like to see the above issues addressed before we return to these
changes.

llvm-svn: 167222
2012-11-01 09:14:31 +00:00
Chandler Carruth
76f7f4a33e Revert the series of commits starting with r166578 which introduced the
getIntPtrType support for multiple address spaces via a pointer type,
and also introduced a crasher bug in the constant folder reported in
PR14233.

These commits also contained several problems that should really be
addressed before they are re-committed. I have avoided reverting various
cleanups to the DataLayout APIs that are reasonable to have moving
forward in order to reduce the amount of churn, and minimize the number
of commits that were reverted. I've also manually updated merge
conflicts and manually arranged for the getIntPtrType function to stay
in DataLayout and to be defined in a plausible way after this revert.

Thanks to Duncan for working through this exact strategy with me, and
Nick Lewycky for tracking down the really annoying crasher this
triggered. (Test case to follow in its own commit.)

After discussing with Duncan extensively, and based on a note from
Micah, I'm going to continue to back out some more of the more
problematic patches in this series in order to ensure we go into the
LLVM 3.2 branch with a reasonable story here. I'll send a note to
llvmdev explaining what's going on and why.

Summary of reverted revisions:

r166634: Fix a compiler warning with an unused variable.
r166607: Add some cleanup to the DataLayout changes requested by
         Chandler.
r166596: Revert "Back out r166591, not sure why this made it through
         since I cancelled the command. Bleh, sorry about this!
r166591: Delete a directory that wasn't supposed to be checked in yet.
r166578: Add in support for getIntPtrType to get the pointer type based
         on the address space.
llvm-svn: 167221
2012-11-01 08:07:29 +00:00
Michael Liao
677865ac64 Cleanup another place redundant SP maintained
llvm-svn: 167209
2012-11-01 03:47:50 +00:00
Shuxin Yang
4762eb1825 (For X86) Enhancement to add-carray/sub-borrow (adc/sbb) optimization.
The adc/sbb optimization is to able to convert following expression
into a single adc/sbb instruction:
  (ult) ... = x + 1 // where the ult is unsigned-less-than comparison
  (ult) ... = x - 1

  This change is to flip the "x >u y" (i.e. ugt comparison) in order 
to expose the adc/sbb opportunity.

llvm-svn: 167180
2012-10-31 23:11:48 +00:00
Nadav Rotem
e3083d1688 Fix a bug in the cost calculation of vector casts. Detect situations where bitcasts cost zero.
llvm-svn: 167170
2012-10-31 20:52:26 +00:00
Akira Hatanaka
245eaafd42 [mips] Set isAsCheapAsAMove flag on ADDiu and DADDiu, which enables
re-materialization of immediate loads.

llvm-svn: 167153
2012-10-31 18:37:55 +00:00
Reed Kotler
82a7f09a30 Implement ADJCALLSTACKUP and ADJCALLSTACKDOWN
llvm-svn: 167107
2012-10-31 05:21:10 +00:00
Craig Topper
d7d1914a7d Add scalar forms of FMA4 VFNMSUB/VFNMADD to folding tables. Patch from Cameron McInally.
llvm-svn: 167106
2012-10-31 04:59:46 +00:00
Michael Liao
299b55458f Clean up redundant SP register maintained in X86 TLI
llvm-svn: 167104
2012-10-31 04:14:09 +00:00