Bill Wendling
9c0a4581e4
Make the URL a link instead.
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llvm-svn: 156655
2012-05-11 22:38:33 +00:00
Michael J. Spencer
6161587c9f
[Support/StringRef] Add find_last_not_of and {r,l,}trim.
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llvm-svn: 156652
2012-05-11 22:08:50 +00:00
Bill Wendling
55c91b69ec
Remove extraneous ; and the resulting warning.
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llvm-svn: 156649
2012-05-11 21:56:04 +00:00
Bill Wendling
e349cbad11
Add mention of Glasgow Haskell Compiler.
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llvm-svn: 156648
2012-05-11 21:42:37 +00:00
Chad Rosier
4a65a2a197
[fast-isel] Add support for selecting @llvm.trap().
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llvm-svn: 156646
2012-05-11 21:33:49 +00:00
Brendon Cahoon
ea214cd0af
Updated instruction table due to addded intrinsics.
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llvm-svn: 156644
2012-05-11 21:10:16 +00:00
Sirish Pande
d0570c5bdd
Remove warnings from HexagonVLIWPacketizer.
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llvm-svn: 156636
2012-05-11 20:00:34 +00:00
Duncan Sands
a97949f6c4
Some release notes for dragonegg.
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llvm-svn: 156635
2012-05-11 19:59:43 +00:00
Brendon Cahoon
90dddafa44
Hexagon constant extender support.
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Patch by Jyotsna Verma.
llvm-svn: 156634
2012-05-11 19:56:59 +00:00
Chad Rosier
4141fa486f
Typo.
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llvm-svn: 156633
2012-05-11 19:43:29 +00:00
Chad Rosier
72bd34ca71
[fast-isel] Remove -disable-arm-fast-isel option. -fast-isel=0 suffices. Minor cleanup.
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llvm-svn: 156632
2012-05-11 19:40:25 +00:00
Sirish Pande
4590b341e2
Hexagon V5 intrinsics support.
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llvm-svn: 156631
2012-05-11 19:39:13 +00:00
Jakob Stoklund Olesen
041239982f
Defer computation of SuperRegs.
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Don't compute the SuperRegs list until the sub-register graph is
completely finished. This guarantees that the list of super-registers is
properly topologically ordered, and has no duplicates.
llvm-svn: 156629
2012-05-11 19:01:01 +00:00
Chad Rosier
c20de37076
[fast-isel] Cleaner fix for when we're unable to handle a non-double multi-reg
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retval. Hoists check before emitting the call to avoid unnecessary work.
rdar://11430407
PR12796
llvm-svn: 156628
2012-05-11 18:51:55 +00:00
Nuno Lopes
11d6ecb6db
objectsize: add a few more tests and fix a bug
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llvm-svn: 156625
2012-05-11 18:25:29 +00:00
Chad Rosier
4c5904bbe5
[fast-isel] Rather then assert (or segfault in a non-asserts build), fall back
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to selection DAG isel if we're unable to handle a non-double multi-reg retval.
rdar://11430407
PR12796
llvm-svn: 156622
2012-05-11 17:41:06 +00:00
Chad Rosier
5d178a402f
The return type is an unsigned, not a bool.
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llvm-svn: 156621
2012-05-11 16:41:38 +00:00
Manman Ren
9c31a160a8
Add space before an open parenthesis in control flow statements.
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llvm-svn: 156620
2012-05-11 15:36:46 +00:00
Preston Gurd
691d5f1eb6
Added X86 Atom latencies to X86InstrMMX.td.
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llvm-svn: 156615
2012-05-11 14:27:12 +00:00
Stepan Dyatkovskiy
a1652c65c7
PR1255: ConstantRangesSet and CRSBuilder classes moved from include/llvm to include/llvm/Support.
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llvm-svn: 156613
2012-05-11 10:34:23 +00:00
Hans Wennborg
ea694231ad
Fix test/CodeGen/X86/tls-pie.ll.
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llvm-svn: 156612
2012-05-11 10:19:54 +00:00
Hans Wennborg
a5a417fcd3
Implement initial-exec TLS model for 32-bit PIC x86
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This fixes a TODO from 2007 :) Previously, LLVM would emit the wrong
code here (see the update to test/CodeGen/X86/tls-pie.ll).
llvm-svn: 156611
2012-05-11 10:11:01 +00:00
Silviu Baranga
5138c169b1
Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions.
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llvm-svn: 156609
2012-05-11 09:28:27 +00:00
Silviu Baranga
dad5ffc779
Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate.
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llvm-svn: 156608
2012-05-11 09:10:54 +00:00
Rafael Espindola
b550a4f952
Fix a use after free when the streamer is destroyed. Fixes pr12622.
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llvm-svn: 156606
2012-05-11 03:42:13 +00:00
Akira Hatanaka
e579470749
Fix a misleading comment.
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llvm-svn: 156603
2012-05-11 01:45:15 +00:00
Jim Grosbach
289783c78d
Tidy up. Trailing whitespace.
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llvm-svn: 156602
2012-05-11 01:41:30 +00:00
Jim Grosbach
f588df5936
Tidy up. Trailing whitespace.
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llvm-svn: 156601
2012-05-11 01:39:13 +00:00
Eli Friedman
1746bfc50e
Fix a minor logic mistake transforming compares in instcombine. PR12514.
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llvm-svn: 156600
2012-05-11 01:32:59 +00:00
Manman Ren
c82d0e71b9
ARM: peephole optimization to remove cmp instruction
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This patch will optimize the following cases:
sub r1, r3 | sub r1, imm
cmp r3, r1 or cmp r1, r3 | cmp r1, imm
bge L1
TO
subs r1, r3
bge L1 or ble L1
If the branch instruction can use flag from "sub", then we can replace
"sub" with "subs" and eliminate the "cmp" instruction.
rdar: 10734411
llvm-svn: 156599
2012-05-11 01:30:47 +00:00
Dan Gohman
ed475ad173
Define a new intrinsic, @llvm.debugger. It will be similar to __builtin_trap(),
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but it generates int3 on x86 instead of ud2.
llvm-svn: 156593
2012-05-11 00:19:32 +00:00
Eric Christopher
c2a56d46fc
Allow unique_file to take a mode for file permissions, but default
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to user only read/write.
Part of rdar://11325849
llvm-svn: 156591
2012-05-11 00:07:44 +00:00
Chad Rosier
8107a3524e
Fix intendation.
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llvm-svn: 156589
2012-05-10 23:38:07 +00:00
Jakob Stoklund Olesen
5a51c567a1
Compute secondary sub-registers.
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The sub-registers explicitly listed in SubRegs in the .td files form a
tree. In a complicated register bank, it is possible to have
sub-register relationships across sub-trees. For example, the ARM NEON
double vector Q0_Q1 is a tree:
Q0_Q1 = [Q0, Q1], Q0 = [D0, D1], Q1 = [D2, D3]
But we also define the DPair register D1_D2 = [D1, D2] which is fully
contained in Q0_Q1.
This patch teaches TableGen to find such sub-register relationships, and
assign sub-register indices to them. In the example, TableGen will
create a dsub_1_dsub_2 sub-register index, and add D1_D2 as a
sub-register of Q0_Q1.
This will eventually enable the coalescer to handle copies of skewed
sub-registers.
llvm-svn: 156587
2012-05-10 23:27:10 +00:00
Nuno Lopes
415911a5c7
objectsize: add support for GEPs with non-constant indexes
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add an additional parameter to InstCombiner::EmitGEPOffset() to force it to *not* emit operations with NUW flag
llvm-svn: 156585
2012-05-10 23:17:35 +00:00
Preston Gurd
236873fb5d
Added X86 Atom latencies for instructions in X86InstrInfo.td.
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llvm-svn: 156579
2012-05-10 21:58:35 +00:00
Eric Christopher
dbb26083e5
Add support for the 'X' inline asm operand modifier.
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Patch by Jack Carter.
llvm-svn: 156577
2012-05-10 21:48:22 +00:00
Andrew Trick
e907a8bc0e
misched: Print machineinstrs with -debug-only=misched
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llvm-svn: 156576
2012-05-10 21:06:21 +00:00
Andrew Trick
19b39882d9
misched: tracing register pressure heuristics.
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llvm-svn: 156575
2012-05-10 21:06:19 +00:00
Andrew Trick
ba6b818855
misched: Add register pressure backoff to ConvergingScheduler.
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Prioritize the instruction that comes closest to keeping pressure
under the target's limit. Then prioritize instructions that avoid
increasing the max pressure in the scheduled region. The max pressure
heuristic is a tad aggressive. Later I'll fix it to consider the
unscheduled pressure as well.
WIP: This is mostly functional but untested and not likely to do much good yet.
llvm-svn: 156574
2012-05-10 21:06:16 +00:00
Andrew Trick
949bbbecd6
misched: Release only unscheduled nodes into ReadyQ.
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llvm-svn: 156573
2012-05-10 21:06:14 +00:00
Andrew Trick
50028ab54e
misched: Added ReadyQ container wrapper for Top and Bottom Queues.
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llvm-svn: 156572
2012-05-10 21:06:12 +00:00
Andrew Trick
828845f0e8
misched: Introducing Top and Bottom register pressure trackers during scheduling.
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llvm-svn: 156571
2012-05-10 21:06:10 +00:00
Sirish Pande
a621830325
Hexagon V5 Support - V5 td file.
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llvm-svn: 156569
2012-05-10 20:24:28 +00:00
Sirish Pande
7fbfe4a1d6
Hexagon V5 FP Support.
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llvm-svn: 156568
2012-05-10 20:20:25 +00:00
Andrew Trick
bfd4d328b1
RegPressure: API for speculatively checking instruction pressure.
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Added getMaxExcessUpward/DownwardPressure. They somewhat abuse the
tracker by speculatively handling an instruction out of order. But it
is convenient for now. In the future, we will cache each instruction's
pressure contribution to make this efficient.
llvm-svn: 156561
2012-05-10 19:11:52 +00:00
Andrew Trick
980318a1e5
RegPressure: fix array index iteration style.
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llvm-svn: 156560
2012-05-10 19:11:49 +00:00
Dan Gohman
8b1a3cec89
Teach DeadStoreElimination to eliminate exit-block stores with phi addresses.
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llvm-svn: 156558
2012-05-10 18:57:38 +00:00
Manman Ren
5abcae1320
Revert: 156550 "ARM: peephole optimization to remove cmp instruction"
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This commit broke an external linux bot and gave a compile-time warning.
llvm-svn: 156556
2012-05-10 18:49:43 +00:00
Jakob Stoklund Olesen
e762a8379f
Precompute lists of explicit sub-registers and indices.
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The .td files specify a tree of sub-registers. Store that tree as
ExplicitSubRegs lists in CodeGenRegister instead of extracting it from
the Record when needed.
llvm-svn: 156555
2012-05-10 17:46:18 +00:00