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Commit Graph

189161 Commits

Author SHA1 Message Date
Bill Wendling
c9e75264ee Add parentheses to silence warning 2019-12-20 12:52:36 -08:00
Petr Hosek
dcf1bd6c94 [llvm-symbolizer] Support reading options from environment
llvm-symbolizer is used by sanitizers to symbolize errors discovered by
sanitizer, but there's no way to pass options to llvm-symbolizer since
the tool is invoked directly by the sanitizer runtime. Therefore, we
don't have a way to pass options needed to find debug symbols such as
-dsym-hint or -debug-file-directory. This change enables reading options
from the LLVM_SYMBOLIZER_OPTS in addition to command line which can be
used to pass those additional options to llvm-symbolizer invocations
made by sanitizer runtime.

Differential Revision: https://reviews.llvm.org/D71668
2019-12-20 12:47:27 -08:00
LLVM GN Syncbot
113b26aae4 [gn build] Port 82923c71efa 2019-12-20 20:35:49 +00:00
Philip Reames
26f411e5f6 More style cleanups following rG14fc20ca6282 [NFC]
Demote member functions to static functions where possible
Use early continue/early return to reduce nesting
Clarify comments slightly.
Reuse previously define expression in one case.
2019-12-20 12:19:33 -08:00
Philip Reames
2d3e7f7066 Fix a memory leak introduced w/the instruction padding support in rG14fc20ca6282
Should have caught this in review, but only noticed when addressing post commit style items.  We were creating a new instance of the X86MCInstrInfo class, and then never reclaiming the memory.  This wasn't even conditional on the new off by default flags, so it was an unconditional leak.
2019-12-20 12:04:07 -08:00
Philip Reames
1f8262a87a Comment and adjust style in the newly introduced MCBoundaryAlignFragment infrastructure. More to follow. 2019-12-20 12:04:07 -08:00
Philip Reames
e0244827fe Align branches within 32-Byte boundary (NOP padding)
WARNING: If you're looking at this patch because you're looking for a full
performace mitigation of the Intel JCC Erratum, this is not it!

This is a preliminary patch on the patch towards mitigating the performance
regressions caused by Intel's microcode update for Jump Conditional Code
Erratum.  For context, see:
https://www.intel.com/content/www/us/en/support/articles/000055650.html

The patch adds the required assembler infrastructure and command line options
needed to exercise the logic for INTERNAL TESTING.  These are NOT public flags,
and should not be used for anything other than LLVM's own testing/debugging
purposes.  They are likely to change both in spelling and meaning.

WARNING: This patch is knowingly incorrect in some cornercases.  We need, and
do not yet provide, a mechanism to selective enable/disable the padding.
Conversation on this will continue in parellel with work on extending this
infrastructure to support prefix padding.

The goal here is to have the assembler align specific instructions such that
they neither cross or end at a 32 byte boundary.  The impacted instructions are:
a. Conditional jump.
b. Fused conditional jump.
c. Unconditional jump.
d. Indirect jump.
e. Ret.
f. Call.

The new options for llvm-mc are:
    -x86-align-branch-boundary=NUM aligns branches within NUM byte boundary.
    -x86-align-branch=TYPE[+TYPE...] specifies types of branches to align.

A new MCFragment type, MCBoundaryAlignFragment, is added, which may emit
NOP to align the fused/unfused branch.

alignBranchesBegin inserts MCBoundaryAlignFragment before instructions,
alignBranchesEnd marks the end of the branch to be aligned,
relaxBoundaryAlign grows or shrinks sizes of NOP to align the target branch.

Nop padding is disabled when the instruction may be rewritten by the linker,
such as TLS Call.

Process Note: I am landing a patch by skan as it has been LGTMed, and
continuing to iterate on the review is simply slowing us down at this point.
We can and will continue to iterate in tree.

Patch By: skan
Differential Revision: https://reviews.llvm.org/D70157
2019-12-20 11:35:50 -08:00
Fangrui Song
19fb620829 [PPC32] Emit R_PPC_PLTREL24 for calls to dso_local ifunc
static void *ifunc(void) __attribute__((ifunc("resolver")));
  void foo() { ifunc(); }

The relocation produced by the ifunc() call:

1. gcc -msecure-plt -fPIC => R_PPC_PLTREL24 r_addend=0x8000
2. gcc -msecure-plt -PIE => R_PPC_PLTREL24 r_addend=0x8000
3. clang -msecure-plt -fPIC => R_PPC_PLTREL24 r_addend=0x8000
4. clang -msecure-plt -fPIE => R_PPC_REL24

4 is incorrect. The R_PPC_REL24 needs a call stub due to ifunc. If this
relocation is mixed with other R_PPC_PLTREL24(r_addend=0x8000) in a
function, both GNU ld and lld (after D71621 fix) may produce a wrong
result.

This patch fixes 4 to use R_PPC_PLTREL24, which matches GCC.
Both GNU ld and lld (after D71621) will be happy.

Reviewed By: sfertile

Differential Revision: https://reviews.llvm.org/D71649
2019-12-20 11:32:02 -08:00
Craig Topper
54c65a9a69 [X86] Fix a KNL miscompile caused by combineSetCC swapping LHS/RHS variables before a later use.
The setcc operands are copied into LHS and RHS variables at the top of the function. We also capture the condition code.

A later piece of code swaps the operands and changing the CC variable as part of a canonicalization to make some other checks simpler. But we might not make the transform we canonicalized for. So we continue on through the function where we can use the swapped LHS/RHS variables and access the original condition code operand instead of the modified CC variable. This leads to a setcc being created with the original condition code, but with swapped operands.

To mitigate this, this patch does a couple things. The LHS/RHS/CC variables are made const to keep them from being modified like this again. The transform that needs the swap now uses temporary copies of the variables. And the transform that used the original condition code operand has been altered to use the CC variable we cached originally. Either of these changes are enough to fix the issue, but doing both to make this code very safe.

I also considered rewriting the swap code in some way to check both permutations without explicitly swapping or needing temporary variables, but held off on that.

Differential Revision: https://reviews.llvm.org/D71736
2019-12-20 11:24:45 -08:00
Danilo Carvalho Grael
ab60031c47 [AArch64][SVE] Replace integer immediate intrinsics with splat vector variant
Summary: Replace the integer immediate intrisics with splat vector variants so they can be applied as optimizations for the C/C++ intrinsics.

Reviewers: sdesmalen, huntergr, rengolin, efriedma, c-rhodes, mgudim, kmclaughlin

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits, amehsan

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D71614
2019-12-20 13:52:19 -05:00
Jonas Paulsson
fa76304be1 [SystemZ] Add a mapping from "select register" to "load on condition" (2-addr).
The SELR(Mux) instructions can be converted to two-address form as LOCR(Mux)
instructions whenever one of the sources are the same reg as dest. By adding
this mapping in getTwoOperandOpcode(), we get:

- Two-address hints in getRegAllocationHints() for select register
  instructions.

- No need anymore for special handling in SystemZShortenInst.cpp -
  shortenSelect() removed.

The two-address hints are now added before the GRX32 hints, which should be
preferred.

Review: Ulrich Weigand
https://reviews.llvm.org/D68870
2019-12-20 10:44:58 -08:00
Evgenii Stepanov
809f567590 llvm-symbolizer: support DW_FORM_loclistx locations.
Summary:
With -gdwarf-5 local variable locations are emitted as DW_FORM_loclistx
form instead of the regular DW_FORM_sec_offset. Teach
DWARFDie::getLocations to understand the new format and use it in
llvm-symbolizer "FRAME" command.

Reviewers: pcc, jdoerfert

Subscribers: srhines, aprantl, hiraditya, rupprecht, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70756
2019-12-20 10:36:14 -08:00
Jordan Rupprecht
a9ab626582 Temporarily revert "Reapply [LVI] Normalize pointer behavior" and "[LVI] Restructure caching"
This reverts commits 7e18aeba5062cd4324a9efb7bc25c9dbc4a34c2c (D70376) 21fbd5587cdfa11dabb3aeb0ead2d3d5fd0b490d (D69914) due to increased memory usage.
2019-12-20 10:25:57 -08:00
Jonas Paulsson
61f35cd2aa [SystemZ] Bugfix and improve the handling of CC values.
It was recently discovered that the handling of CC values was actually broken
since overflow was not properly handled ('nsw' flag not checked for).

Add and sub instructions now have a new target specific instruction flag
named SystemZII::CCIfNoSignedWrap. It means that the CC result can be used
instead of a compare with 0, but only if the instruction has the 'nsw' flag
set.

This patch also adds the improvements of conversion to logical instructions
and the analyzing of add with immediates, to be able to eliminate more
compares.

Review: Ulrich Weigand
https://reviews.llvm.org/D66868
2019-12-20 10:20:23 -08:00
Victor Campos
bbb6f6b671 Revert "[ARM] Improve codegen of volatile load/store of i64"
This reverts commit bbcf1c3496ce2bd1ed87e8fb15ad896e279633ce.
2019-12-20 18:08:24 +00:00
Sanjay Patel
3bb4bc53e1 [InstCombine] add tests for cast+gep; NFC
PR44321:
https://bugs.llvm.org/show_bug.cgi?id=44321
2019-12-20 10:52:23 -05:00
Ulrich Weigand
9da855799b [SystemZ][FPEnv] Enable strict vector FP extends/truncations
The back-end currently has special DAGCombine code to detect
cases where two floating-point extend or truncate operations
can be combined into a single vector operation.

This patch extends that support to also handle strict FP operations.

Note that currently only the case where both operations have the
same input chain are supported.  This already suffices to cover
the common case where the operations result from scalarizing a
non-legal vector type.  More general cases can be supported in
the future.
2019-12-20 15:36:56 +01:00
Paul Walker
887a76b062 [AArch64][SVE] Correct intrinsics and patterns for logical predicate instructions
In general SVE intrinsics are considered predicated and merging
with everything else having suitable decoration.  For predicated
zeroing operations (like the predicate logical instructions) we
use the "_z" suffix.  After this change all intrinsics use their
expected names (i.e. orr instead of or and eor instead of xor).

I've removed intrinsics and patterns for condition code setting
instructions as that data is not returned as part of the intrinsic.
The expectation is to ask for a cc flag explicitly.

For example:
  a = and_z(pg, p1, p2)
  cc = ptest_<flag>(pg, a)

With the code generator expected to use "s" variants of instructions
when available.

Differential Revision: https://reviews.llvm.org/D71715
2019-12-20 14:22:27 +00:00
Tom Weaver
6bf5a34797 [OPT-DBG] Teach DbgEntityHistoryCalculator about meta-instructions.
The calculator was considering instructions such as KILLs as clobbers
of a physical address. This is wrong as meta instructions such as KILLs
produce no output in the final program and thus don't clobber or change
any physical location's value. As a result they're safe to ignore whilst
calculating location list ranges.

reviewers: aprantl, vsk

diff revision: https://reviews.llvm.org/D70497

fixes: https://bugs.llvm.org/show_bug.cgi?id=38753
2019-12-20 14:03:34 +00:00
Sanjay Patel
17125e834f [AArch64] add more tests for extract-bitcast-splat; NFC
Goes with D71672 - we should be able to handle casting to
a wider type as well as casting to a narrower type.
2019-12-20 08:57:23 -05:00
Ayal Zaks
4b218d0f3e [LV] Strip wrap flags from vectorized reductions
A sequence of additions or multiplications that is known not to wrap, may wrap
if it's order is changed (i.e., reassociated). Therefore when vectorizing
integer sum or product reductions, their no-wrap flags need to be removed.

Fixes PR43828

Patch by Denis Antrushin

Differential Revision: https://reviews.llvm.org/D69563
2019-12-20 14:48:53 +02:00
Cullen Rhodes
d8d4261ca4 [AArch64][SVE] Fold constant multiply of element count
Summary:
E.g.

  %0 = tail call i64 @llvm.aarch64.sve.cntw(i32 31)
  %mul = mul i64 %0, <const>

Should emit:

  cntw    x0, all, mul #<const>

For <const> in the range 1-16.

Patch by Kerry McLaughlin

Reviewers: sdesmalen, huntergr, dancgr, rengolin, efriedma

Reviewed By: sdesmalen

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D71014
2019-12-20 11:58:00 +00:00
Andrzej Warzynski
650025e84c [AArch64][SVE] Add intrnisics for saturating scalar arithmetic
Summary:
The following intrnisics are added:
  * @llvm.aarch64.sve.sqdec{b|h|w|d|p}
  * @llvm.aarch64.sve.sqinc{b|h|w|d|p}
  * @llvm.aarch64.sve.uqdec{b|h|w|d|p}
  * @llvm.aarch64.sve.uqinc{b|h|w|d|p}

For every intrnisic there a scalar variants (with n32 or n64 suffix) and
vector variants (no suffix).

Reviewers: sdesmalen, rengolin, efriedma

Reviewed By: sdesmalen, efriedma

Subscribers: eli.friedman, tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D71252
2019-12-20 11:09:40 +00:00
Cullen Rhodes
07e2ea5e7e Recommit "[AArch64][SVE] Add permutation and selection intrinsics"
Recommit 23c28c40436143006be740533375c036d11c92cd (reverted in
dcb48f50bdfa0fa47b62d089b6ed999d857fc9f8) with a fix for an assert
"Request for a fixed size on a scalable object" being triggered in
`LowerSVEIntrinsicEXT`. The fix is to call `getKnownMinSize` on the
TypeSize object.
2019-12-20 10:45:17 +00:00
Andrzej Warzynski
03e8b97579 [AArch64][SVE] Add intrinsics for binary narrowing operations
Summary:
The following intrinsics for binary narrowing shift righ operations are
added:
  * @llvm.aarch64.sve.shrnb
  * @llvm.aarch64.sve.uqshrnb
  * @llvm.aarch64.sve.sqshrnb
  * @llvm.aarch64.sve.sqshrunb
  * @llvm.aarch64.sve.uqrshrnb
  * @llvm.aarch64.sve.sqrshrnb
  * @llvm.aarch64.sve.sqrshrunb
  * @llvm.aarch64.sve.shrnt
  * @llvm.aarch64.sve.uqshrnt
  * @llvm.aarch64.sve.sqshrnt
  * @llvm.aarch64.sve.sqshrunt
  * @llvm.aarch64.sve.uqrshrnt
  * @llvm.aarch64.sve.sqrshrnt
  * @llvm.aarch64.sve.sqrshrunt

Reviewers: sdesmalen, rengolin, efriedma

Reviewed By: efriedma

Subscribers: tschuett, kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D71552
2019-12-20 10:20:30 +00:00
Sam Parker
3ddecf8632 [ARM][MVE] Fixes for tail predication.
1) Fix an issue with the incorrect value being used for the number of
   elements being passed to [d|w]lstp. We were trying to check that
   the value was available at LoopStart, but this doesn't consider
   that the last instruction in the block could also define the
   register. Two helpers have been added to RDA for this.
2) Insert some code to now try to move the element count def or the
   insertion point so that we can perform more tail predication.
3) Related to (1), the same off-by-one could prevent us from
   generating a low-overhead loop when a mov lr could have been
   the last instruction in the block.
4) Fix up some instruction attributes so that not all the
   low-overhead loop instructions are labelled as branches and
   terminators - as this is not true for dls/dlstp.

Differential Revision: https://reviews.llvm.org/D71609
2019-12-20 09:34:18 +00:00
David Spickett
033afbf4d8 Re-land "[cmake] Add dependency on llvm-dwarfdump to llvm-locstats"
This reverts commit f8e2ab3cd347cb7fb959ea0ece795f4eb347094c.
2019-12-20 09:11:07 +00:00
Sam Parker
b8b0b4e20a [ARM][MVE] Tail predicate in the presence of vcmp
Record the discovered VPT blocks while checking for validity and, for
now, only handle blocks that begin with VPST and not VPT. We're now
allowing more than one instruction to define vpr, but each block must
somehow be predicated using the vctp. This leaves us with several
scenarios which need fixing up:
1) A VPT block with is only predicated by the vctp and has no
   internal vpr defs.
2) A VPT block which is only predicated by the vctp but has an
   internal vpr def.
3) A VPT block which is predicated upon the vctp as well as another
   vpr def.
4) A VPT block which is not predicated upon a vctp, but contains it
   and all instructions within the block are predicated upon in.

The changes needed are, for:
1) The easy one, just remove the vpst and unpredicate the
   instructions in the block.
2) Remove the vpst and unpredicate the instructions up to the
   internal vpr def. Need insert a new vpst to predicate the
   remaining instructions.
3) No nothing.
4) The vctp will be inside a vpt and the instruction will be removed,
   so adjust the size of the mask on the vpst.

Differential Revision: https://reviews.llvm.org/D71107
2019-12-20 08:42:11 +00:00
Sam Parker
3bf04856df [ARM][MVE] Tail predicate bottom/top muls.
Add VMULL and VQDMULL variants to our tail predication white list.

Differential Revision: https://reviews.llvm.org/D71465
2019-12-20 08:33:01 +00:00
Craig Topper
39100bda93 [X86] Make EmitCmp into a static function and explicitly return chain result for STRICT_FCMP. NFCI
The only thing its getting from the X86TargetLowering class is
the subtarget which we can easily pass. This function only has
one call site now since this might help the compiler inline it.

Explicitly return both the flag result and the chain result for
STRICT_FCMP nodes. This removes an assumption in the caller that
getValue(1) is the right way to get the chain.
2019-12-19 23:03:15 -08:00
Craig Topper
0bb47f0f5f [X86] Directly call EmitTest in two places instead of creating a null constant and calling EmitCmp. NFCI
EmitCmp will just immediately call EmitTest and discard the null
constant only to have EmitTest create it again if it doesn't fold.

So just skip all that and go directly to EmitTest.
2019-12-19 23:03:06 -08:00
Lang Hames
80fb117833 [Orc][LLJIT] Re-apply 298e183e813 (use JITLink for LLJIT where supported).
Patch d9220b580b3 fixed the underlying issue that casued 298e183e813 to fail.
2019-12-19 20:42:26 -08:00
Lang Hames
f1bb810112 [JITLink][MachO] Fix common symbol size plumbing.
This fixes the underlying bug that was exposed by 298e183e813.
2019-12-19 20:41:59 -08:00
River Riddle
79f1d6b1a0 [CommandLine] Add template instantiations of cl::parser for long and long long.
This allows cl::opt<int64_t>.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D71729
2019-12-19 17:01:22 -08:00
Craig Topper
a4417ec84b [X86] Add test case for miscompilation of a vector setcc on KNL target. NFC 2019-12-19 16:56:59 -08:00
Jessica Paquette
d0d7cd1383 [lit] Add "from .main import main" back into lit/__init__.py
A refactoring commit (cf252240) removed this line. Removing it broke installing
lit with pip and setup.py.

This adds the line back in so that we can install lit again.

For an example of how this appeared, see:

http://green.lab.llvm.org/green/job/LNT_Tests/5853/

File "/Users/buildslave/jenkins/...s/__init__.py", line 2453, in resolve
    raise ImportError(str(exc))
ImportError: 'module' object has no attribute 'main'
2019-12-19 16:09:27 -08:00
Mircea Trofin
1543ab479e [NFC][InlineCost] Simplify internal inlining cost interface
Summary:
All the use cases of CallAnalyzer use the same call site parameter to
both construct the CallAnalyzer, and then pass to the analysis member.
This change removes this duplication.

Reviewers: davidxl, eraman, Jim

Reviewed By: davidxl

Subscribers: Jim, hiraditya, haicheng, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D71645
2019-12-19 15:32:15 -08:00
Roman Lebedev
d746d62b1a [ValueTracking] isKnownNonZero() should take non-null-ness assumptions into consideration (PR43267)
Summary:
It is pretty common to assume that something is not zero.
Even optimizer itself sometimes emits such assumptions
(e.g. `addAssumeNonNull()` in `PromoteMemoryToRegister.cpp`).

But we currently don't deal with such assumptions :)
The only way `isKnownNonZero()` handles assumptions is
by calling `computeKnownBits()` which calls `computeKnownBitsFromAssume()`.
But `x != 0` does not tell us anything about set bits,
it only says that there are *some* set bits.
So naturally, `KnownBits` does not get populated,
and we fail to make use of this assumption.

I propose to deal with this special case by special-casing it
via adding a `isKnownNonZeroFromAssume()` that returns boolean
when there is an applicable assumption.

While there, we also deal with other predicates,
mainly if the comparison is with constant.

Fixes [[ https://bugs.llvm.org/show_bug.cgi?id=43267 | PR43267 ]].

Differential Revision: https://reviews.llvm.org/D71660
2019-12-20 01:47:57 +03:00
Roman Lebedev
3540c93924 [ValueTracking] isValidAssumeForContext(): CxtI itself also must transfer execution to successor
This is a pretty rare case, when CxtI and assume are
in the same basic block, with assume being located later.

We were already checking that assumption was guaranteed to be
executed, but we omitted CxtI itself from consideration,
and as the test (miscompile) shows, that is incorrect.

As noted in D71660 review by @nikic.
2019-12-20 01:47:57 +03:00
Roman Lebedev
271922b995 [NFC][InstCombine] Add a test for assume-induced miscompile
@escape() may throw here, we don't know that assumption, which is located
afterwards in the same block, is executed, therefore %load arg of
call to @escape() can not be marked as non-null.

As noted in D71660 review by @nikic.
2019-12-20 01:47:56 +03:00
Vedant Kumar
880c712961 HotColdSplitting: Do not outline within noreturn functions
A function marked `noreturn` may contain unreachable terminators: these
should not be considered cold, as the function may be a trampoline.

rdar://58068594
2019-12-19 14:06:24 -08:00
Philip Reames
fe5f5af18a [StackMaps] Be explicit about label formation [NFC] (try 2)
Recommit after making the same API change in non-x86 targets.  This has been build for all targets, and tested for effected ones.  Why the difference?  Because my disk filled up when I tried make check for all.

For auto-padding assembler support, we'll need to bundle the label with the instructions (nops or call sequences) so that they don't get separated.  This just rearranges the code to make the upcoming change more obvious.
2019-12-19 14:05:30 -08:00
Tim Northover
cda3149bb7 ConstrainedFP: use API compatible with opaque pointers.
This just updates an IRBuilder interface to take Functions instead of
Values so the type can be derived, and fixes some callsites in Clang to
call the updated API.
2019-12-19 21:50:47 +00:00
LLVM GN Syncbot
9541184165 [gn build] Port 3075cd5c9fc 2019-12-19 21:33:15 +00:00
Eric Christopher
b77d05f0b5 Temporarily Revert "[Dsymutil][Debuginfo][NFC] Refactor dsymutil to separate DWARF optimizing part 2."
as it causes a layering violation/dependency cycle:

llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp -> llvm/DebugInfo/DWARF/DWARFExpression.h
llvm/include/llvm/DebugInfo/DWARF/DWARFOptimizer.h -> llvm/CodeGen/NonRelocatableStringpool.h

This reverts commit abc7f6800df8a1f40e1e2c9ccce826abb0208284.
2019-12-19 13:29:02 -08:00
jasonliu
44b7f48d64 [XCOFF][AIX] Fix for missing of undefined symbols from symbol table
Summary:
When we use undefined symbol with its qualname, we are not able
to generate that symbol because of the logic of early "continue"
that skip the qualname symbol. This patch fixes it.

Differential revision: https://reviews.llvm.org/D71667
2019-12-19 21:20:33 +00:00
Eric Christopher
29b1810e56 Temporarily Revert "[StackMaps] Be explicit about label formation [NFC]"
as it broke the aarch64 build.

This reverts commit bc7595d934b958ab481288d7b8e768fe5310be8f.
2019-12-19 12:52:40 -08:00
Philip Reames
5ea77424b5 [StackMaps] Be explicit about label formation [NFC]
For auto-padding assembler support, we'll need to bundle the label with the instructions (nops or call sequences) so that they don't get separated.  This just rearranges the code to make the upcoming change more obvious.
2019-12-19 12:38:44 -08:00
Philip Reames
074409d2ef [FaultMaps] Make label formation a bit more explicit [NFC]
This is in advance of assembler padding directives support where we'll need to bundle the label w/the corresponding faulting instruction to avoid padding being inserted between.
2019-12-19 12:38:44 -08:00
Craig Topper
7b023f35a7 [LegalizeDAG] Add return to the strict node handling in PromoteLegalINT_TO_FP to prevent an invalid strict fp node from being created by falling into non-strict code path. 2019-12-19 11:39:50 -08:00