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14332 Commits

Author SHA1 Message Date
Owen Anderson
a1a10ed5c6 Thumb2 POP's don't allow the PC as an operand, and PUSH's don't allow the SP either. 
llvm-svn: 139542
 2011-09-12 21:28:46 +00:00
Bruno Cardoso Lopes
64e2e852f9 Revert the wrong part of r139528, and fix testcases. 
llvm-svn: 139541
 2011-09-12 21:24:07 +00:00
Owen Anderson
0081444d87 Fix encoding of PC-relative LDRSHW with an immediate offset. 
llvm-svn: 139537
 2011-09-12 20:36:51 +00:00
Andrew Trick
bf1bc9a077 Conditionalize indvars tests that rely on SCEV expansion of geps, 
which is relevant with canonical IVs. Anything else being checked by
these tests is already covered by early CSE.

llvm-svn: 139535
 2011-09-12 20:26:34 +00:00
Bruno Cardoso Lopes
c67e996fc3 Not sure how CMPPS and CMPPD had already ever worked, I guess it didn't. 
However with this fix it does now.

Basically the operand order for the x86 target specific node
is not the same as the instruction, but since the intrinsic need that
specific order at the instruction definition, just change the order
during legalization. Also, there were some wrong invertions of condition
codes, such as GE => LE, GT => LT, fix that too. Fix PR10907.

llvm-svn: 139528
 2011-09-12 19:30:40 +00:00
Owen Anderson
05ef2c122d Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered. 
llvm-svn: 139522
 2011-09-12 18:56:30 +00:00
Andrew Trick
efe8cdcf20 Removing indvars tests that directly test canonical IVs and nothing else. 
llvm-svn: 139518
 2011-09-12 18:33:08 +00:00
Andrew Trick
09cf4287c2 Rename -disable-iv-rewrite to -enable-iv-rewrite=false in preparation for default change. 
llvm-svn: 139517
 2011-09-12 18:28:44 +00:00
Eli Friedman
08926ecbfb Fix mistake in test runline. 
llvm-svn: 139505
 2011-09-12 17:32:58 +00:00
Andrew Trick
19f9e653cd Test case for r139453, WidenIV::GetExtendedOperandRecurrence. 
llvm-svn: 139504
 2011-09-12 17:20:57 +00:00
Richard Osborne
962b1ca071 Associate a MemOperand with LDWCP nodes introduced during ISel. 
This information is required if we want LDWCP to be hoisted out of loops.

llvm-svn: 139495
 2011-09-12 14:43:23 +00:00
Craig Topper
5ffd0cb080 Fix disassembling of one of the register/register forms of MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877. 
llvm-svn: 139486
 2011-09-11 23:19:54 +00:00
Craig Topper
a9b27eecc9 Fix disassembling of reverse register/register forms of ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV. 
llvm-svn: 139485
 2011-09-11 21:41:45 +00:00
Craig Topper
8361de67b5 Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP disassembling to ignore OpSize and REX.W. 
llvm-svn: 139484
 2011-09-11 20:23:20 +00:00
Eli Friedman
2275f7612e Really un-XFAIL the testcase, like I said I would in r139458. 
llvm-svn: 139459
 2011-09-10 02:02:27 +00:00
Richard Trieu
0485e133f2 Fixed an assert from: 
assert("not implemented for target shuffle node");

to:

  assert(0 && "not implemented for target shuffle node");

This causes a test failure in CodeGen/X86/palignr.ll which has
been marked as XFAIL for the time being.
Test failure filed at PR10901.

llvm-svn: 139454
 2011-09-10 01:26:21 +00:00
Jim Grosbach
52492b1cf3 Thumb2 parsing and encoding for MOV(immediate). 
Some aliases for MOV(register) also to keep existing T1 tests happy when
run in thumbv7 mode.

llvm-svn: 139440
 2011-09-10 00:15:36 +00:00
Akira Hatanaka
a8f0f7babb Fix test cases. 
Generate code for Mips32r1 unless a Mips32r2 feature is tested.

llvm-svn: 139433
 2011-09-09 23:14:58 +00:00
Owen Anderson
9cd21ce8c9 LDM writeback is not allowed if Rn is in the target register list. 
llvm-svn: 139432
 2011-09-09 23:13:33 +00:00
Owen Anderson
dbe77fc5a1 Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands. 
llvm-svn: 139422
 2011-09-09 22:24:36 +00:00
Owen Anderson
a7838cb723 Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches. 
llvm-svn: 139415
 2011-09-09 21:48:23 +00:00
Eli Friedman
4bae1c4f70 Make the SelectionDAG verify that all the operands of BUILD_VECTOR have the same type. Teach DAGCombiner::visitINSERT_VECTOR_ELT not to make invalid BUILD_VECTORs. Fixes PR10897. 
llvm-svn: 139407
 2011-09-09 21:04:06 +00:00
Akira Hatanaka
f65d050693 Drop support for Mips1 and Mips2. 
llvm-svn: 139405
 2011-09-09 20:45:50 +00:00
Nadav Rotem
ccb46031e6 Implement vector-select support for avx256. Refactor the vblend implementation to have tablegen match the instruction by the node type 
llvm-svn: 139400
 2011-09-09 20:29:17 +00:00
Jim Grosbach
6225a96bf5 Thumb2 assembly parsing and encoding for MLA and MLS. 
llvm-svn: 139399
 2011-09-09 20:24:45 +00:00
Jim Grosbach
5f87c06a64 Thumb2 assembly parsing and encoding for MCR, MCR2, MCRR, MCRR2. 
llvm-svn: 139397
 2011-09-09 20:19:28 +00:00
Jim Grosbach
f310295150 Tidy up formatting a bit. 
llvm-svn: 139396
 2011-09-09 20:17:49 +00:00
Jim Grosbach
f7d8e569b3 Thumb2 assembly parsing and encoding for LSL. 
llvm-svn: 139395
 2011-09-09 20:05:38 +00:00
Jim Grosbach
69e67f206d Thumb2 assembly parsing and encoding for LDRT. 
llvm-svn: 139393
 2011-09-09 20:02:15 +00:00
Jim Grosbach
abd54fb32c Thumb2 assembly parsing and encoding for LDRSHT. 
llvm-svn: 139392
 2011-09-09 20:01:18 +00:00
Jim Grosbach
c6aa5be010 Thumb2 assembly parsing and encoding for LDRSH. 
llvm-svn: 139391
 2011-09-09 19:54:30 +00:00
Jim Grosbach
022da868a5 Thumb2 assembly parsing and encoding for LDRSBT. 
llvm-svn: 139390
 2011-09-09 19:49:06 +00:00
Jim Grosbach
915ba5189e Thumb2 assembly parsing and encoding for LDRSB. 
llvm-svn: 139389
 2011-09-09 19:42:40 +00:00
Jim Grosbach
6faf547463 Thumb2 assembly parsing and encoding for LDRH. 
llvm-svn: 139386
 2011-09-09 19:13:53 +00:00
Jim Grosbach
26f684d4ff Shuffle a bit. 
llvm-svn: 139385
 2011-09-09 19:09:54 +00:00
Akira Hatanaka
17df2dfe8c Drop support for Allegrex. Allegrex implements a variant of Mips2. 
llvm-svn: 139383
 2011-09-09 19:00:51 +00:00
Jim Grosbach
eb2d668899 Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH. 
llvm-svn: 139381
 2011-09-09 18:37:27 +00:00
Jim Grosbach
1091b2913d Add FIXME. 
llvm-svn: 139371
 2011-09-09 16:45:31 +00:00
Duncan Sands
6fc4c521c9 Mark the eh.typeid.for intrinsic as being 'const', which it is inside 
any given function.  As pointed out by John McCall, this is needed to
have redundant eh.typeid.for tests be eliminated in the presence of
cleanups.

llvm-svn: 139360
 2011-09-09 07:50:37 +00:00
Craig Topper
23adfa4738 Add disassembler test for Intel syntax. Tests r139353. 
llvm-svn: 139356
 2011-09-09 06:35:44 +00:00
Akira Hatanaka
e1eb015eb9 Change default target architecture from Mips1 to Mips32r1 in preparation for 
removing support for Mips1 and Mips2. 

This change and the ones that follow have been discussed with and approved by
Bruno.

llvm-svn: 139344
 2011-09-09 01:13:27 +00:00
Devang Patel
ba2d56b1ef Directly point debug info to the stack slot of the arugment, instead of trying to keep track of vreg in which it the arugment is copied. The LiveDebugVariable can keep track of variable's ranges. 
llvm-svn: 139330
 2011-09-08 22:59:09 +00:00
Owen Anderson
d7127e0c27 Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block. 
llvm-svn: 139328
 2011-09-08 22:42:49 +00:00
Jim Grosbach
9f150bfedf Thumb2 assembly parsing and encoding for LDRD(immediate). 
Refactor operand handling for STRD as well. Tests for that forthcoming.

llvm-svn: 139322
 2011-09-08 22:07:06 +00:00
Bruno Cardoso Lopes
54962ac233 Add a AVX version of a simple i64 -> f64 bitcast. This could be 
triggered using llc with -O0, which wouldn't let it be folded and
expose the lack of this pattern.

llvm-svn: 139320
 2011-09-08 21:52:33 +00:00
Bruno Cardoso Lopes
50596b096c Reapply testcase from r139309! 
llvm-svn: 139318
 2011-09-08 21:05:43 +00:00
Kevin Enderby
16f9df1f05 Fix a Darwin x86_64 special case of a jmp to a temporary symbol from an atom 
without a base symbol that must not have a relocation entry.

llvm-svn: 139316
 2011-09-08 20:53:44 +00:00
Bruno Cardoso Lopes
3ecc7a69fd Remove this crashing test, until I figure out what's going wrong here 
llvm-svn: 139309
 2011-09-08 18:32:36 +00:00
Bruno Cardoso Lopes
74a67e22b0 Add AVX versions of blend vector operations and fix some issues noticed 
in Nadav's r139285 and r139287 commits.

1) Rename vsel.ll to a more descriptive name
2) Change the order of BLEND operands to "Op1, Op2, Cond", this is
necessary because PBLENDVB is already used in different places with
this order, and it was being emitted in the wrong way for vselect
3) Add AVX patterns and tests for the same SSE41 instructions

llvm-svn: 139305
 2011-09-08 18:05:08 +00:00
Bruno Cardoso Lopes
84c53e3965 Fix PR10844: Add patterns to cover non foldable versions of X86vzmovl. 
Triggered using llc -O0. Also fix some SET0PS patterns to their AVX
forms and test it on the testcase.

llvm-svn: 139304
 2011-09-08 18:05:02 +00:00
Jim Grosbach
222a102bd1 Add tests for Thumb2 LDRB indexed addressing w/ writeback. 
llvm-svn: 139292
 2011-09-08 16:49:36 +00:00
Nadav Rotem
fd68584146 This test is already covered by llvm/trunk/test/CodeGen/X86/vsel.ll 
llvm-svn: 139288
 2011-09-08 08:43:23 +00:00
Nadav Rotem
dbfa2c8810 add a testcase for the previous patch 
llvm-svn: 139287
 2011-09-08 08:31:31 +00:00
Nadav Rotem
b461f2190e Add X86-SSE4 codegen support for vector-select. 
llvm-svn: 139285
 2011-09-08 08:11:19 +00:00
Eli Friedman
6e9cab83b0 Fix the logic in BasicAliasAnalysis::aliasGEP for comparing GEP's with variable differences so that it actually does something sane. Fixes PR10881. 
llvm-svn: 139276
 2011-09-08 02:23:31 +00:00
Jim Grosbach
5ac3aa158b Thumb2 assembly parsing and encoding for LDR post-indexed. 
More cleanup of the general indexed addressing T2 instructions. Still more to
do, especially for stores.

llvm-svn: 139272
 2011-09-08 01:01:32 +00:00
Jim Grosbach
1aa191032a Thumb2 assembly parsing and encoding for LDR pre-indexed w/ writeback. 
Adjust encoding of writeback load/store instructions to better reflect the
way the operand types are represented.

llvm-svn: 139270
 2011-09-08 00:39:19 +00:00
Jim Grosbach
8b54d19514 Thumb2 assembly parsing and encoding for LDRBT. 
llvm-svn: 139267
 2011-09-07 23:39:14 +00:00
Jim Grosbach
7482c11b79 Thumb2 assembly parsing and encoding for LDRB(register). 
llvm-svn: 139266
 2011-09-07 23:17:00 +00:00
Jim Grosbach
a3ff9eeb85 Thumb2 assembly parsing and encoding for LDR(register). 
llvm-svn: 139264
 2011-09-07 23:10:15 +00:00
Jim Grosbach
d640c62856 Thumb2 assembly parsing and encoding for LDRB(immediate). 
llvm-svn: 139258
 2011-09-07 21:41:25 +00:00
Jim Grosbach
deb3c78242 Thumb2 assembly parsing and encoding for LDR(literal). 
Need branch relocation support to distinguish this encoding from the
16-bit Thumb1 encoding w/o the explicit .w suffix. That comes later, though.

llvm-svn: 139257
 2011-09-07 21:33:16 +00:00
Owen Anderson
26467730c1 Create Thumb2 versions of STC/LDC, and reenable the relevant tests. 
llvm-svn: 139256
 2011-09-07 21:10:42 +00:00
Jim Grosbach
53b836a088 Add tests for Thumb2 LDR(immediate) from r139254. 
llvm-svn: 139255
 2011-09-07 21:06:46 +00:00
Jim Grosbach
054b346e46 Thumb2 parsing and encoding for LDMDB. 
llvm-svn: 139251
 2011-09-07 19:57:53 +00:00
James Molloy
ac057f13a5 Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. 
llvm-svn: 139250
 2011-09-07 19:42:28 +00:00
Eli Friedman
9ea5599729 Fix atomic load and store on x86 to pass -verify-machineinstrs (and possibly fix some subtle bugs involving passes which check mayStore()). 
This isn't exactly ideal, but it is good enough for the moment.

llvm-svn: 139245
 2011-09-07 18:48:32 +00:00
Jim Grosbach
f5f321c4ce Update test for 139243 
llvm-svn: 139244
 2011-09-07 18:40:06 +00:00
Jim Grosbach
20689d28e7 Thumb2 parsing and encoding for LDMIA. 
Choose 32-bit vs. 16-bit encoding when there's no .w suffix in post-processing
as match classes are insufficient to handle the context-sensitiveness of
the writeback operand's legality for the 16-bit encodings.

llvm-svn: 139242
 2011-09-07 18:05:34 +00:00
Owen Anderson
4106b9fb31 Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed. 
llvm-svn: 139240
 2011-09-07 17:55:19 +00:00
Duncan Sands
b027f19035 When inlining exception handling code into another function, ensure that 
duplicate tests are eliminated (for example if the two functions both have
a catch clause catching the same type, ensure the redundant one is removed).
Note that it would probably be safe to say that eh.typeid.for is 'const',
but since two calls to it with the same argument can give different results
(but only if the calls are in different functions), it seems more correct to
mark it only 'pure'; this doesn't get in the way of the optimization.

llvm-svn: 139236
 2011-09-07 16:44:14 +00:00
Duncan Sands
8df5170d0d Another forgotten trampoline testcase. 
llvm-svn: 139230
 2011-09-07 10:05:14 +00:00
Duncan Sands
ccd8b589f7 Forgot to add this trampoline testcase. 
llvm-svn: 139229
 2011-09-07 09:21:38 +00:00
Eli Friedman
6a45370c0f Relax the MemOperands on atomics a bit. Fixes -verify-machineinstrs failures for atomic laod/store on ARM. 
(The fix for the related failures on x86 is going to be nastier because we actually need Acquire memoperands attached to the atomic load instrs, etc.)

llvm-svn: 139221
 2011-09-07 02:23:42 +00:00
Devang Patel
f4483238b6 While sinking machine instructions, sink matching DBG_VALUEs also otherwise live debug variable pass will drop DBG_VALUEs on the floor. 
llvm-svn: 139208
 2011-09-07 00:07:58 +00:00
Owen Anderson
483f94e8d1 Teach BasicAA about the aliasing properties of memset_pattern16. 
Fixes PR10872 and <rdar://problem/10065079>.

llvm-svn: 139204
 2011-09-06 23:33:25 +00:00
Jim Grosbach
14720bed32 Thumb2 parsing and encoding for ISB. 
llvm-svn: 139200
 2011-09-06 22:53:27 +00:00
Jim Grosbach
521a061450 Thumb2 parsing and encoding for EOR. 
llvm-svn: 139199
 2011-09-06 22:44:50 +00:00
Jim Grosbach
463bf279d6 Thumb2 parsing and encoding for DSB. 
llvm-svn: 139194
 2011-09-06 22:19:40 +00:00
Jim Grosbach
276e51888c Thumb2 parsing and encoding for DMB. 
llvm-svn: 139193
 2011-09-06 22:14:58 +00:00
Nick Lewycky
4e3daabb26 Disable these tests harder. They're XFAIL'd, but that means they still run, and 
these tests all infinitely recurse, bringing my system down into swapping hell.

llvm-svn: 139192
 2011-09-06 22:08:18 +00:00
Jim Grosbach
c0aaa747a1 Thumb2 parsing and encoding for DBG. 
llvm-svn: 139191
 2011-09-06 22:06:40 +00:00
Jim Grosbach
4258d5ffba Thumb2 parsing and encoding for CMN and CMP. 
llvm-svn: 139188
 2011-09-06 21:44:58 +00:00
Nick Lewycky
8203bcfd03 This transform only handles two-operand AddRec's. Prevent it from trying to 
handle anything more complex. Fixes PR10383 again!

llvm-svn: 139186
 2011-09-06 21:42:18 +00:00
Jim Grosbach
45bc30cc7e Thumb2 parsing and encoding for CLZ. 
llvm-svn: 139177
 2011-09-06 20:44:17 +00:00
Jim Grosbach
b5dcc965a7 Thumb2 parsing and encoding for CLREX. 
llvm-svn: 139172
 2011-09-06 20:27:04 +00:00
Owen Anderson
23820ebb17 Port more encoding tests over to Thumb2 decoding tests. 
llvm-svn: 139171
 2011-09-06 20:26:34 +00:00
Jim Grosbach
3399db069a Thumb2 parsing and encoding for CDP/CDP2. 
llvm-svn: 139168
 2011-09-06 20:12:23 +00:00
Evan Cheng
891e9696ea Fix fall outs from my recent change on how carry bit is modeled during isel. 
Now the 'S' instructions, e.g. ADDS, treat S bit as optional operand as well.
Also fix isel hook to correctly set the optional operand.
rdar://10073745

llvm-svn: 139157
 2011-09-06 18:52:20 +00:00
Owen Anderson
ca0326a423 Try again at r138809 (make DSE more aggressive in removing dead stores at the end of a function), now with less deleting stores before memcpy's. 
llvm-svn: 139150
 2011-09-06 18:14:09 +00:00
Jakob Stoklund Olesen
7994269719 Atomic pseudos don't use (as in read) CPSR. They clobber it. 
llvm-svn: 139148
 2011-09-06 17:40:35 +00:00
Duncan Sands
6939ae53ac Split the init.trampoline intrinsic, which currently combines GCC's 
init.trampoline and adjust.trampoline intrinsics, into two intrinsics
like in GCC.  While having one combined intrinsic is tempting, it is
not natural because typically the trampoline initialization needs to
be done in one function, and the result of adjust trampoline is needed
in a different (nested) function.  To get around this llvm-gcc hacks the
nested function lowering code to insert an additional parent variable
holding the adjust.trampoline result that can be accessed from the child
function.  Dragonegg doesn't have the luxury of tweaking GCC code, so it
stored the result of adjust.trampoline in the memory GCC set aside for
the trampoline itself (this is always available in the child function),
and set up some new memory (using an alloca) to hold the trampoline.
Unfortunately this breaks Go which allocates trampoline memory on the
heap and wants to use it even after the parent has exited (!).  Rather
than doing even more hacks to get Go working, it seemed best to just use
two intrinsics like in GCC.  Patch mostly by Sanjoy Das.

llvm-svn: 139140
 2011-09-06 13:37:06 +00:00
Nick Lewycky
3823432a57 The logic inside getMulExpr to simplify {a,+,b}*{c,+,d} was wrong, which was 
visible given a=b=c=d=1, on iteration #1 (the second iteration). Replace it with
correct math. Fixes PR10383!

llvm-svn: 139133
 2011-09-06 05:05:14 +00:00
Nick Lewycky
18c0b01a56 Revert r139126 due to selfhost failures reported by buildbots. 
llvm-svn: 139130
 2011-09-06 02:43:13 +00:00
Nick Lewycky
30dcc754df Teach SCEV to report a max backedge count in one interesting case in 
HowFarToZero; the case for a canonical loop.

llvm-svn: 139126
 2011-09-05 23:25:16 +00:00
Benjamin Kramer
ec933b857e InstSimplify: Don't try to replace an extractvalue/insertvalue pair with the original value if types don't match. 
Fixes clang selfhost.

llvm-svn: 139120
 2011-09-05 18:16:19 +00:00
Duncan Sands
d883f9f371 Delete trivial landing pads that just continue unwinding the caught 
exception.

llvm-svn: 139117
 2011-09-05 12:57:57 +00:00
Duncan Sands
a74d10bb60 Add some simple insertvalue simplifications, for the purpose of cleaning 
up do-nothing exception handling code produced by dragonegg.

llvm-svn: 139113
 2011-09-05 06:52:48 +00:00
Dan Gohman
cbadb0f92c Revert r129875, XFAILing this test for arm, since the fix was reverted. 
llvm-svn: 139058
 2011-09-03 00:14:24 +00:00
Jakob Stoklund Olesen
ef8527b836 Pseudo CMOV instructions don't clobber EFLAGS. 
The explanation about a 0 argument being materialized as xor is no
longer valid.  Rematerialization will check if EFLAGS is live before
clobbering it.

The code produced by X86TargetLowering::EmitLoweredSelect does not
clobber EFLAGS.

This causes one less testb instruction to be generated in the cmov.ll
test case.

llvm-svn: 139057
 2011-09-02 23:52:55 +00:00
Jim Grosbach
68afe301fc Thumb2 parsing and encoding for CBZ/CBNZ. 
llvm-svn: 139054
 2011-09-02 23:46:10 +00:00
Jim Grosbach
fb5e64e731 Thumb2 parsing and encoding for BXJ. 
llvm-svn: 139053
 2011-09-02 23:43:09 +00:00
Jim Grosbach
2ea035b027 Thumb2 parsing and encoding for BIC. 
llvm-svn: 139052
 2011-09-02 23:37:54 +00:00
Jim Grosbach
588f94c09b Thumb2 parsing and encoding for BFI. 
llvm-svn: 139051
 2011-09-02 23:28:46 +00:00
Jim Grosbach
7a45cb2b33 Thumb2 parsing and encoding for BFC. 
llvm-svn: 139050
 2011-09-02 23:25:46 +00:00
Jim Grosbach
44483a9ba5 Thumb2 parsing and encoding of B instruction. 
Tweak handling of IT blocks a bit to enable this. The differentiation between
B and Bcc needs special sauce.

llvm-svn: 139049
 2011-09-02 23:22:08 +00:00
Bill Wendling
145872a92c Try to eliminate the use of the 'unwind' instruction. 
llvm-svn: 139046
 2011-09-02 22:41:11 +00:00
Eli Friedman
383a3c76b2 Don't fast-isel for atomic load/store; some cases require extra handling missing from fast-isel. 
llvm-svn: 139044
 2011-09-02 22:33:24 +00:00
Jim Grosbach
ba4ceeaae6 Thumb2 parsing and encoding for ASR. 
For other shift and rotate instructions, too. Tests for those forthcoming
as I work my way through the ISA.

llvm-svn: 139040
 2011-09-02 21:28:54 +00:00
Bill Wendling
267bc5089a Better fix for this testcase. Update it to the new EH scheme entirely. 
llvm-svn: 139039
 2011-09-02 21:27:08 +00:00
Bill Wendling
a4f9142ad4 Update for new EH stuff. (I'm not sure if this is 100% correct.) 
llvm-svn: 139038
 2011-09-02 21:24:17 +00:00
Andrew Trick
f449c87835 Test case update for unroll-scev. 
llvm-svn: 139037
 2011-09-02 21:21:03 +00:00
Kevin Enderby
90a1526592 Change X86 disassembly to print immediates values as signed by default. Special 
case those instructions that the immediate is not sign-extend.  radr://8795217

llvm-svn: 139028
 2011-09-02 20:01:23 +00:00
Jim Grosbach
cbf37eebff Thumb2 parsing and encoding for AND (register). 
llvm-svn: 139021
 2011-09-02 18:41:35 +00:00
Jim Grosbach
dd0421034a Thumb2 parsing and encoding for ADD (register). 
llvm-svn: 139017
 2011-09-02 18:14:46 +00:00
Duncan Sands
33f33411e8 Darwin wants ctors/dtors to be ordered the other way round to linux. 
llvm-svn: 139015
 2011-09-02 18:07:19 +00:00
Kevin Enderby
edfcba2f3c Fix the disassembly of the X86 "crc32w %ax, %eax" instruction. Bug 10702. 
llvm-svn: 139014
 2011-09-02 18:03:03 +00:00
Jim Grosbach
32cf633f1c Tests for Thumb2 AND (immediate) instruction. 
llvm-svn: 139013
 2011-09-02 17:44:27 +00:00
Jakub Staszak
fef314417c Extra CHECK-NOT to make sure that GVN transform works properly. 
llvm-svn: 139012
 2011-09-02 17:40:39 +00:00
Andrew Trick
88877293d1 -unroll-scev flag removal 
llvm-svn: 139010
 2011-09-02 17:36:14 +00:00
Jim Grosbach
5b43c7fe81 Add FIXME. Thumb2 ADR encoding choice is non-trivial. 
llvm-svn: 139008
 2011-09-02 17:21:59 +00:00
Jakub Staszak
132e24bf28 ConstantVector returns arbitrary value for the wrong index. 
This fixes PR10813.

llvm-svn: 139006
 2011-09-02 15:43:43 +00:00
Jakub Staszak
b82758ae9b Compare type size instead of type _store_ size to make sure that BitCastInst 
will be valid. This fixes PR10820.

llvm-svn: 139005
 2011-09-02 14:57:37 +00:00
Kalle Raiskila
7c154fe467 Pass signed (not unsigned) 10 bit field to SPU 'ori' instruction. 
llvm-svn: 139004
 2011-09-02 10:05:01 +00:00
Craig Topper
316c7bfe37 Make IC_VEX* not inherit from IC_*. Prevents instructions with no VEX form from disassembling to their non-VEX form. Also prevents weak filter collisons that were keeping valid VEX instructions from decoding properly. Make VEX_L* not inherit from VEX_* because the VEX.L bit always important. This stops packed int VEX encodings from being disassembled when specified with VEX.L=1. Fixes PR10831 and PR10806. 
llvm-svn: 138997
 2011-09-02 04:17:54 +00:00
Bill Wendling
a96c532f67 Update to new EH scheme. 
llvm-svn: 138989
 2011-09-02 01:25:11 +00:00
Dan Gohman
6d0230847c Revert r131152, r129796, r129761. This code is currently considered 
to be unreliable on platforms which require memcpy calls, and it is
complicating broader legalize cleanups. It is hoped that these cleanups
will make memcpy byval easier to implement in the future.

llvm-svn: 138977
 2011-09-01 23:07:08 +00:00
Benjamin Kramer
bd939ad83e Don't drop alignment info on local common symbols. 
- On COFF the .lcomm directive has an alignment argument.
- On ELF we fall back to .local + .comm

Based on a patch by NAKAMURA Takumi.

Fixes PR9337, PR9483 and PR10128.

llvm-svn: 138976
 2011-09-01 23:04:27 +00:00
Eli Friedman
2f99e7b97a Fix test; sorry for any inconvenience. 
llvm-svn: 138966
 2011-09-01 21:25:42 +00:00
Eli Friedman
00a62b2122 Fix an issue with the IR sink pass found by inspection. (I'm not sure anyone is actually using this, but might as well fix it since I found the issue.) 
llvm-svn: 138965
 2011-09-01 21:21:24 +00:00
Eli Friedman
a154929048 Add missing newline. 
llvm-svn: 138964
 2011-09-01 21:20:11 +00:00
Benjamin Kramer
4ed9810e77 XFAIL this test on arm until the backend is fixed. 
llvm-svn: 138955
 2011-09-01 18:40:03 +00:00
Benjamin Kramer
ca7001eedb This test depends on cmov being available. 
llvm-svn: 138954
 2011-09-01 18:40:01 +00:00
Jakob Stoklund Olesen
c26e2e6221 Permit remat of partial register defs when it is safe. 
An instruction may define part of a register where the other bits are
undefined. In that case, it is safe to rematerialize the instruction.
For example:

  %vreg2:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:%noreg, %vreg2<imp-def>

The extra <imp-def> operand indicates that the instruction does not read
the other parts of the virtual register, so a remat is safe.

This patch simply allows multiple def operands for the virtual register.
It is MI->readsVirtualRegister() that determines if we depend on a
previous value so remat is impossible.

llvm-svn: 138953
 2011-09-01 18:27:51 +00:00
Jim Grosbach
36ea6726dd ARM 'rscs' mnemonic is carry-setting 'rsc', not 'rs' with a 'cs' condition code. 
llvm-svn: 138952
 2011-09-01 18:22:13 +00:00
Bruno Cardoso Lopes
10f234f1a7 Fix vbroadcast matching logic to early unmatch if the node doesn't have 
only one use. Fix PR10825.

llvm-svn: 138951
 2011-09-01 18:15:06 +00:00
Owen Anderson
d8157fabfb t2Bcc is allowed to have a predicate without a preceding IT instruction. 
llvm-svn: 138946
 2011-09-01 17:47:45 +00:00
Jakob Stoklund Olesen
bc000bf219 Prevent remat of partial register redefinitions. 
An instruction that redefines only part of a larger register can never
be rematerialized since the virtual register value depends on the old
value in other parts of the register.

This was fixed for the inline spiller in r138794.  This patch fixes the
problem for all register allocators, and includes a small test case.

<rdar://problem/10032939>

llvm-svn: 138944
 2011-09-01 17:18:50 +00:00
Bill Wendling
196167f986 Update to new EH scheme. 
llvm-svn: 138933
 2011-09-01 01:28:25 +00:00
Bill Wendling
68ada987a1 Update to new EH scheme. 
llvm-svn: 138928
 2011-09-01 01:08:21 +00:00
Bill Wendling
6ebcfea89e Update to new EH scheme. 
llvm-svn: 138927
 2011-09-01 01:02:41 +00:00
Bill Wendling
0b2e131798 Update some tests to the new EH scheme. 
llvm-svn: 138925
 2011-09-01 00:58:03 +00:00
Andrew Trick
e5d7c0d111 PreRA scheduler should avoid cloning compares. 
Added canClobberReachingPhysRegUse() to handle a particular pattern in
which a two-address instruction could be forced to interfere with
EFLAGS, causing a compare to be unnecessarilly cloned.
Fixes rdar://problem/5875261

llvm-svn: 138924
 2011-09-01 00:54:31 +00:00
Jim Grosbach
2b04342a91 Thumb2 assembly parsing and encoding for ADD(immediate). 
llvm-svn: 138922
 2011-09-01 00:28:52 +00:00
Bill Wendling
f3c35d972d Reenable test. 
llvm-svn: 138916
 2011-08-31 23:08:05 +00:00
Bill Wendling
fc2565227c Revert accidental commit 
llvm-svn: 138915
 2011-08-31 23:07:46 +00:00
Eli Friedman
5e68a0aca8 Disable this test until Bill fixes it properly. 
llvm-svn: 138914
 2011-08-31 23:03:30 +00:00
Bill Wendling
8b764c6aa5 Update to new EH scheme. 
llvm-svn: 138908
 2011-08-31 21:50:07 +00:00
Bill Wendling
e540c593ec Update to new EH scheme. 
llvm-svn: 138906
 2011-08-31 21:44:24 +00:00
Bill Wendling
66b613c8b9 Remove old declare statements. 
llvm-svn: 138905
 2011-08-31 21:41:20 +00:00