Evan Cheng
ca1e6eea8e
Joining a live interval of a physical register with a virtual one can turn out
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to be really bad. Once they are joined they are not broken apart. Also, physical
intervals cannot be spilled!
Added a heuristic as a workaround for this. Be careful coalescing with a
physical register if the virtual register uses are "far". Check if there are
uses in the same loop as the source (copy instruction). Check if it is in the
loop preheader, etc.
llvm-svn: 35134
2007-03-17 09:27:35 +00:00
Evan Cheng
65d69fe08d
Use SmallSet instead of std::set.
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llvm-svn: 35133
2007-03-17 08:53:30 +00:00
Evan Cheng
8552300ab1
If sdisel has decided to sink GEP index expression into any BB. Replace all uses
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in that BB.
llvm-svn: 35132
2007-03-17 08:22:49 +00:00
Devang Patel
2dabb16eac
Support 'I' inline asm constraint.
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llvm-svn: 35129
2007-03-17 00:13:28 +00:00
Lauro Ramos Venancio
f756184c5e
Only ARMv6 has BSWAP.
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Fix MultiSource/Applications/aha test.
llvm-svn: 35128
2007-03-16 22:54:16 +00:00
Evan Cheng
77099bef05
Turn on GEP index sinking by default.
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llvm-svn: 35127
2007-03-16 18:32:30 +00:00
Evan Cheng
449900b988
Stupid bug.
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llvm-svn: 35126
2007-03-16 17:50:20 +00:00
Bill Wendling
8ced23ee5a
And now support for MMX logical operations.
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llvm-svn: 35125
2007-03-16 09:44:46 +00:00
Evan Cheng
c3e7d4b884
Sink a binary expression into its use blocks if it is a loop invariant
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computation used as GEP indexes and if the expression can be folded into
target addressing mode of GEP load / store use types.
llvm-svn: 35123
2007-03-16 08:46:27 +00:00
Evan Cheng
4858c6f781
Added isLegalAddressExpression(). Only allows X +/- C for now.
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llvm-svn: 35122
2007-03-16 08:43:56 +00:00
Evan Cheng
ce8b779c6c
Added isLegalAddressExpression hook to test if the given expression can be
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folded into target addressing mode for the given type.
llvm-svn: 35121
2007-03-16 08:42:32 +00:00
Nick Lewycky
de44438e24
Add more comments and update to new asm syntax.
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Add new micro-optimizations.
Add icmp predicate snuggling. Given %x ULT 4, "icmp ugt %x, 2" becomes
"icmp eq %x, 3". This doesn't apply in any non-trivial cases yet due to missing
support for NE values in ValueRanges.
llvm-svn: 35119
2007-03-16 02:37:39 +00:00
Bill Wendling
feaff80149
Multiplication support for MMX.
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llvm-svn: 35118
2007-03-15 21:24:36 +00:00
Evan Cheng
ab9145d617
Debugging output stuff.
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llvm-svn: 35117
2007-03-15 21:19:28 +00:00
Evan Cheng
dc6ba035bc
Estimate a cost using the possible number of scratch registers required and use
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it as a late BURR scheduling tie-breaker.
Intuitively, it's good to push down instructions whose results are liveout so
their long live ranges won't conflict with other values which are needed inside
the BB. Further prioritize liveout instructions by the number of operands which
are calculated within the BB.
llvm-svn: 35109
2007-03-14 22:43:40 +00:00
Evan Cheng
00edaa08b5
Under X86-64 large code model, do not emit 32-bit pc relative calls.
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llvm-svn: 35108
2007-03-14 22:11:11 +00:00
Evan Cheng
fc80b5b712
Notes about codegen issues.
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llvm-svn: 35107
2007-03-14 21:03:53 +00:00
Evan Cheng
50a0af3b57
Clean up.
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llvm-svn: 35105
2007-03-14 20:20:19 +00:00
Evan Cheng
2617c8dd3a
Oops.
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llvm-svn: 35104
2007-03-14 19:44:58 +00:00
Evan Cheng
371b8e8fa9
X86-64 JIT is in large code model. Need stubs for direct calls.
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llvm-svn: 35097
2007-03-14 10:51:55 +00:00
Evan Cheng
1092e481ce
x86-64 JIT stub codegen.
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llvm-svn: 35096
2007-03-14 10:48:08 +00:00
Evan Cheng
15de6714a4
Preliminary support for X86-64 JIT stub codegen.
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llvm-svn: 35095
2007-03-14 10:44:30 +00:00
Zhou Sheng
5c6399dab7
ShiftAmt might equal to zero. Handle this situation.
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llvm-svn: 35094
2007-03-14 09:07:33 +00:00
Zhou Sheng
4415c2647e
Enable KnownZero/One.clear().
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llvm-svn: 35093
2007-03-14 03:21:24 +00:00
Evan Cheng
399f56eac2
Try schedule def + use closer whne Sethi-Ullman numbers are the same.
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e.g.
t1 = op t2, c1
t3 = op t4, c2
and the following instructions are both ready.
t2 = op c3
t4 = op c4
Then schedule t2 = op first.
i.e.
t4 = op c4
t2 = op c3
t1 = op t2, c1
t3 = op t4, c2
This creates more short live intervals which work better with the register
allocator.
llvm-svn: 35089
2007-03-13 23:25:11 +00:00
Evan Cheng
7cbde8351a
AM2 can match 2^n +/- 1. e.g. ldr r3, [r2, r2, lsl #2 ]
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llvm-svn: 35088
2007-03-13 21:05:54 +00:00
Evan Cheng
7b24b3e474
Zero is always a legal AM immediate.
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llvm-svn: 35087
2007-03-13 20:37:59 +00:00
Evan Cheng
bd964bd8eb
Correct type info for isLegalAddressImmediate() check.
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llvm-svn: 35086
2007-03-13 20:34:37 +00:00
Nicolas Geoffray
9c77df75ea
Stack and register alignment of call arguments in the ELF ABI
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llvm-svn: 35083
2007-03-13 15:02:46 +00:00
Chris Lattner
efc2339bd7
ifdef out some dead code.
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Fix PR1244 and Transforms/InstCombine/2007-03-13-CompareMerge.ll
llvm-svn: 35082
2007-03-13 14:27:42 +00:00
Zhou Sheng
7cf2811ab3
For expression like
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"APInt::getAllOnesValue(ShiftAmt).zextOrCopy(BitWidth)",
to handle ShiftAmt == BitWidth situation, use zextOrCopy() instead of
zext().
llvm-svn: 35080
2007-03-13 06:40:59 +00:00
Zhou Sheng
14cef9ec74
In APInt version ComputeMaskedBits():
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1. Ensure VTy, KnownOne and KnownZero have same bitwidth.
2. Make code more efficient.
llvm-svn: 35078
2007-03-13 02:23:10 +00:00
Evan Cheng
92712d4884
Implement getTargetLowering() or else LSR won't be using ARM specific hooks.
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llvm-svn: 35077
2007-03-13 01:20:42 +00:00
Evan Cheng
b2a5499d86
More flexible TargetLowering LSR hooks for testing whether an immediate is a legal target address immediate or scale.
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llvm-svn: 35076
2007-03-12 23:37:10 +00:00
Evan Cheng
7767159f08
Updated TargetLowering LSR addressing mode hooks for ARM and Thumb.
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llvm-svn: 35075
2007-03-12 23:30:29 +00:00
Evan Cheng
06d83c8fce
More flexible TargetLowering LSR hooks for testing whether an immediate is a legal target address immediate or scale.
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llvm-svn: 35074
2007-03-12 23:29:01 +00:00
Evan Cheng
0eeb8b59eb
More flexible TargetLowering LSR hooks for testing whether an immediate is
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a legal target address immediate or scale.
llvm-svn: 35073
2007-03-12 23:28:50 +00:00
Evan Cheng
1fcdd7e1e5
Use new TargetLowering addressing modes hooks.
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llvm-svn: 35072
2007-03-12 23:27:37 +00:00
Evan Cheng
4224fa3617
Stupid bug: SSE2 supports v2i64 add / sub.
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llvm-svn: 35070
2007-03-12 22:58:52 +00:00
Reid Spencer
7be576b4b0
Revert the last patch as it violates the conditions of sext/zext.
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llvm-svn: 35068
2007-03-12 18:37:25 +00:00
Jeff Cohen
4e667fd766
Unbreak C++ build.
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llvm-svn: 35067
2007-03-12 17:57:00 +00:00
Jeff Cohen
91930bc4d4
Unbreak VC++ build. Do not use identifiers starting with _ as they are reserved and
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can collide with system defined names. Windows defines _BB, for example.
llvm-svn: 35066
2007-03-12 17:56:27 +00:00
Zhou Sheng
0145067d85
For APInt::z/sext(width), if width == BitWidth, just return *this.
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llvm-svn: 35065
2007-03-12 17:47:45 +00:00
Reid Spencer
d59425085f
Add an APInt version of SimplifyDemandedBits.
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Patch by Zhou Sheng.
llvm-svn: 35064
2007-03-12 17:25:59 +00:00
Reid Spencer
b18f916bbe
Add an APInt version of ShrinkDemandedConstant.
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Patch by Zhou Sheng.
llvm-svn: 35063
2007-03-12 17:15:10 +00:00
Zhou Sheng
c8583ff888
Avoid to assert on "(KnownZero & KnownOne) == 0".
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llvm-svn: 35062
2007-03-12 16:54:56 +00:00
Zhou Sheng
c9c53385b8
In function ComputeMaskedBits():
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1. Replace getSignedMinValue() with getSignBit() for better code readability.
2. Replace APIntOps::shl() with operator<<= for convenience.
3. Make APInt construction more effective.
llvm-svn: 35060
2007-03-12 05:44:52 +00:00
Nick Lewycky
8a08bcfbe7
Add value ranges. Currently inefficient in both execution time and
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optimization power.
llvm-svn: 35058
2007-03-10 18:12:48 +00:00
Anton Korobeynikov
0c2d312725
Use range tests in LowerSwitch, where possible
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llvm-svn: 35057
2007-03-10 16:46:28 +00:00
Nick Lewycky
2af4a3ab17
Add getter methods for the extremes of a ConstantRange.
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llvm-svn: 35056
2007-03-10 15:54:12 +00:00