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Commit Graph

111244 Commits

Author SHA1 Message Date
Elena Demikhovsky
aeb7ff5f14 AVX-512: Added all forms of BLENDM instructions,
intrinsics, encoding tests for AVX-512F and skx instructions.

llvm-svn: 224707
2014-12-22 13:52:48 +00:00
Karthik Bhat
a80b575047 Lower multiply-negate operation to mneg on AArch64
This patch pattern matches code such as-
neg	 w8, w8
mul	 w8, w9, w8
to
mneg	 w8, w8, w9

Review: http://reviews.llvm.org/D6754
llvm-svn: 224706
2014-12-22 13:38:58 +00:00
Rafael Espindola
6ca1e5a091 Convert a few tests to FileCheck. NFC.
llvm-svn: 224705
2014-12-22 13:29:46 +00:00
Rafael Espindola
dbf446fea1 The leak detector is dead, long live asan and valgrind.
In resent times asan and valgrind have found way more memory management bugs
in llvm than the special purpose leak detector.

llvm-svn: 224703
2014-12-22 13:00:36 +00:00
Saleem Abdulrasool
1e8df26ce8 CodeGen: minor style tweaks to SSP
Clean up some style related things in the StackProtector CodeGen.  NFC.

llvm-svn: 224693
2014-12-21 21:52:38 +00:00
Craig Topper
387f6219e6 [X86] Add hasSideEffects = 0 to CALLpcrel16. This matches what is inferred from patterns for the 32-bit version.
llvm-svn: 224692
2014-12-21 20:05:06 +00:00
Matt Arsenault
92400a8e42 Enable (sext x) == C --> x == (trunc C) combine
Extend the existing code which handles this for zext. This makes this
more useful for targets with ZeroOrNegativeOne BooleanContent and
obsoletes a custom combine SI uses for i1 setcc (sext(i1), 0, setne)
since the constant will now be shrunk to i1.

llvm-svn: 224691
2014-12-21 16:48:42 +00:00
Craig Topper
719eb172c2 [X86] Swap operand order in Intel syntax on a bunch of aliases.
llvm-svn: 224687
2014-12-20 23:05:59 +00:00
Craig Topper
f7146f3087 [X86] Swap operand order of imul aliases in Intel syntax. Also disable printing of the alias instead of the real instruction.
llvm-svn: 224686
2014-12-20 23:05:57 +00:00
Craig Topper
09c08f1eff [X86] Remove '*' from asm strings in far call/jump aliases for Intel syntax.
llvm-svn: 224685
2014-12-20 23:05:55 +00:00
Craig Topper
4acc85cd8b [X86] Don't swap the order of segment and offset in immediate form of far call/jump in Intel syntax.
llvm-svn: 224684
2014-12-20 23:05:52 +00:00
Saleem Abdulrasool
b5d3c242bc CodeGen: constify and use range loop for SSP
Use range-based for loop and constify the iterators.  NFC.

llvm-svn: 224683
2014-12-20 21:37:51 +00:00
Saleem Abdulrasool
5b457858a7 ARM: further improve deprecated diagnosis (LDM)
The ARM ARM states:
  LDM/LDMIA/LDMFD:
    The SP can be in the list. However, ARM deprecates using these instructions
    with SP in the list.

    ARM deprecates using these instructions with both the LR and the PC in the
    list.

  LDMDA/LDMFA/LDMDB/LDMEA/LDMIB/LDMED:
    The SP can be in the list. However, instructions that include the SP in the
    list are deprecated.

    Instructions that include both the LR and the PC in the list are deprecated.

  POP:
    The SP can only be in the list before ARMv7. ARM deprecates any use of ARM
    instructions that include the SP, and the value of the SP after such an
    instruction is UNKNOWN.

    ARM deprecates the use of this instruction with both the LR and the PC in
    the list.

Attempt to diagnose use of deprecated forms of these instructions.  This mirrors
the previous changes to diagnose use of the deprecated forms of STM in ARM mode.

llvm-svn: 224682
2014-12-20 20:25:36 +00:00
David Majnemer
45ac06f549 strnlen isn't available on some platforms, use StringRef instead
llvm-svn: 224679
2014-12-20 08:24:43 +00:00
Craig Topper
d6845c2d5a [X86] Immediate forms of far call/jump are not valid in x86-64.
llvm-svn: 224678
2014-12-20 07:43:27 +00:00
David Majnemer
ee1d92da94 This should have been part of r224676.
llvm-svn: 224677
2014-12-20 04:48:34 +00:00
David Majnemer
3da9d34415 InstCombine: Squash an icmp+select into bitwise arithmetic
(X & INT_MIN) == 0 ? X ^ INT_MIN : X  into  X | INT_MIN
(X & INT_MIN) != 0 ? X ^ INT_MIN : X  into  X & INT_MAX

This fixes PR21993.

llvm-svn: 224676
2014-12-20 04:45:35 +00:00
David Majnemer
46b6fd2884 InstSimplify: Don't bother if getScalarSizeInBits returns zero
getScalarSizeInBits returns zero when the comparison operands are not
integral.  No functionality change intended.

llvm-svn: 224675
2014-12-20 04:45:33 +00:00
David Majnemer
763dde8503 Simplify the code
No functionality change intended.

llvm-svn: 224673
2014-12-20 03:29:59 +00:00
Eric Fiselier
91f01064d8 Split executeShTest into two parts so that it can be better leveraged by libc++
llvm-svn: 224672
2014-12-20 03:23:53 +00:00
David Majnemer
e2cf8f21e0 InstSimplify: Optimize away pointless comparisons
(X & INT_MIN) ? X & INT_MAX : X  into  X & INT_MAX
(X & INT_MIN) ? X : X & INT_MAX  into  X
(X & INT_MIN) ? X | INT_MIN : X  into  X
(X & INT_MIN) ? X : X | INT_MIN  into  X | INT_MIN

llvm-svn: 224669
2014-12-20 03:04:38 +00:00
Chandler Carruth
e9116958a3 [SROA] Run clang-format over the entire SROA pass as I wrote it before
much of the glory of clang-format, and now any time I touch it I risk
introducing formatting changes as part of a functional commit.

Also, clang-format is *way* better at formatting my code than I am.
Most of this is a huge improvement although I reverted a couple of
places where I hit a clang-format bug with lambdas that has been filed
but not (fully) fixed.

llvm-svn: 224666
2014-12-20 02:39:18 +00:00
Chandler Carruth
dbb21c0267 [x86] Change the test added in r223774 to first check the spelling of
the error message for a bogus processor, and then look specifically for
that error message using FileCheck.

I actually tried to write the test this way at first, but drew a blank
on how to ensure the error message stayed in sync (oops). Now that I've
recalled how to do that, this is clearly better.

It also fixes an issue with a malloc implementation that actually prints
to stderr in all cases, which was causing problems for some builders it
seems.

llvm-svn: 224665
2014-12-20 02:19:22 +00:00
Matthias Braun
e80975852e LiveIntervalAnalysis: No kill flags for partially undefined uses.
We must not add kill flags when reading a vreg with some undefined
subregisters, if subreg liveness tracking is enabled.  This is because
the register allocator may reuse these undefined subregisters for other
values which are not killed.

llvm-svn: 224664
2014-12-20 01:54:50 +00:00
Matthias Braun
37888d3929 LiveIntervalAnalysis: cleanup addKills(), NFC
- Use more const modifiers
- Use references for things that can't be nullptr
- Improve some variable names

llvm-svn: 224663
2014-12-20 01:54:48 +00:00
Matthias Braun
f8e2e8dbd5 Unbreak cmake build with shared libraries enabled.
llvm-svn: 224661
2014-12-20 01:51:02 +00:00
Eric Christopher
96836e70d2 Remove unused variable and initialization.
llvm-svn: 224655
2014-12-20 00:07:09 +00:00
Eric Christopher
615cd41da1 Remove unused variable, initializer, and accessor.
llvm-svn: 224650
2014-12-19 23:46:53 +00:00
Matt Arsenault
47c2c0f05a R600: Remove outdated comment
llvm-svn: 224648
2014-12-19 23:29:13 +00:00
Elena Demikhovsky
744da8554e Masked load and store codegen - fixed 128-bit vectors
The codegen failed on 128-bit types on AVX2.
I added patterns and in td files and tests.

llvm-svn: 224647
2014-12-19 23:27:57 +00:00
Matt Arsenault
a3a9080dce R600/SI: Only form min/max with 1 use.
If the condition is used for something else, this increases
the number of instructions.

llvm-svn: 224646
2014-12-19 23:15:30 +00:00
Reid Kleckner
4fb786f123 EH: Sink computation of local PadMap variable into function that uses it
No functionality change.

llvm-svn: 224635
2014-12-19 22:30:08 +00:00
Eric Fiselier
6dd39e2bd7 [LIT] Add JSONMetricValue type to wrap types supported by the json encoder.
Summary:
The following types can be encoded and decoded by the json library:
`dict`, `list`, `tuple`, `str`, `unicode`, `int`, `long`, `float`, `bool`, `NoneType`. 

`JSONMetricValue` can be constructed with any of these types, and used as part of Test.Result.
This patch also adds a toMetricValue function that converts a value into a MetricValue.




Reviewers: ddunbar, EricWF

Reviewed By: EricWF

Subscribers: cfe-commits, llvm-commits

Differential Revision: http://reviews.llvm.org/D6576

llvm-svn: 224628
2014-12-19 22:29:12 +00:00
Kevin Enderby
7664feebc5 Add printing the LC_ROUTINES load commands with llvm-objdump’s -private-headers.
llvm-svn: 224627
2014-12-19 22:25:22 +00:00
Reid Kleckner
be2f2ecb15 Add the ExceptionHandling::MSVC enumeration
It is intended to be used for a family of personality functions that
have similar IR preparation requirements. Typically when interoperating
with MSVC personality functions, bits of functionality need to be
outlined from the main function into helper functions. There is also
usually more than one landing pad per invoke, which does not match the
LLVM IR landingpad representation.

None of this is implemented yet. This change just adds a new enum that
is active for *-windows-msvc and delegates to the EH removal preparation
pass.  No functionality change for other targets.

llvm-svn: 224625
2014-12-19 22:19:48 +00:00
Sanjay Patel
50aab0bca2 Model sqrtss as a binary operation with one source operand tied to the destination (PR14221)
This is a continuation of r167064 ( http://llvm.org/viewvc/llvm-project?view=revision&revision=167064 ).
That patch started to fix PR14221 ( http://llvm.org/bugs/show_bug.cgi?id=14221 ), but it was not completed. 

Differential Revision: http://reviews.llvm.org/D6330

llvm-svn: 224624
2014-12-19 22:16:28 +00:00
Tom Stellard
a24e537705 R600/SI: isLegalOperand() shouldn't check constant bus for SALU instructions
The constant bus restrictions only apply to VALU instructions.  This
enables SIFoldOperands to fold immediates into SALU instructions.

llvm-svn: 224623
2014-12-19 22:15:37 +00:00
Tom Stellard
d0128b6cee R600/SI: Make sure non-inline constants aren't folded into mubuf soffset operand
mubuf instructions now define the soffset field using the SCSrc_32
register class which indicates that only SGPRs and inline constants
are allowed.

llvm-svn: 224622
2014-12-19 22:15:30 +00:00
Yaron Keren
e069d80b3c Remove isSubroutineType test for isCompositeType, getTag() is enough.
llvm-svn: 224621
2014-12-19 22:15:09 +00:00
David Blaikie
58a6d7bb13 Update SmallPtrSet::insert's doc comment to match the new return type
llvm-svn: 224619
2014-12-19 21:45:11 +00:00
Kevin Enderby
213e0f76f1 Add printing the LC_SUB_CLIENT load command with llvm-objdump’s -private-headers.
llvm-svn: 224616
2014-12-19 21:06:24 +00:00
Peter Collingbourne
cebc34e511 CodeGen: do not attempt to invalidate virtual registers for zero-sized phis.
llvm-svn: 224615
2014-12-19 20:50:07 +00:00
Colin LeMahieu
4c325f2cef [Hexagon] Removing old variants of instructions and updating references.
llvm-svn: 224612
2014-12-19 20:29:29 +00:00
Sanjay Patel
7cfa420ae4 merge consecutive stores of extracted vector elements
Add a path to DAGCombiner::MergeConsecutiveStores() 
to combine multiple scalar stores when the store operands
are extracted vector elements. This is a partial fix for
PR21711 ( http://llvm.org/bugs/show_bug.cgi?id=21711 ).

For the new test case, codegen improves from:

   vmovss  %xmm0, (%rdi)
   vextractps      $1, %xmm0, 4(%rdi)
   vextractps      $2, %xmm0, 8(%rdi)
   vextractps      $3, %xmm0, 12(%rdi)
   vextractf128    $1, %ymm0, %xmm0
   vmovss  %xmm0, 16(%rdi)
   vextractps      $1, %xmm0, 20(%rdi)
   vextractps      $2, %xmm0, 24(%rdi)
   vextractps      $3, %xmm0, 28(%rdi)
   vzeroupper
   retq

To:

   vmovups	%ymm0, (%rdi)
   vzeroupper
   retq

Patch reviewed by Nadav Rotem.

Differential Revision: http://reviews.llvm.org/D6698

llvm-svn: 224611
2014-12-19 20:23:41 +00:00
Colin LeMahieu
b1509fe128 [Hexagon] Adding bit extraction and table indexing instructions.
llvm-svn: 224610
2014-12-19 20:01:08 +00:00
Colin LeMahieu
7e0cce8462 [Hexagon] Adding bit insertion instructions.
llvm-svn: 224609
2014-12-19 19:54:38 +00:00
Colin LeMahieu
11b6034e2b [Hexagon] Adding more xtype shift instructions.
llvm-svn: 224608
2014-12-19 19:51:35 +00:00
Kevin Enderby
eb0052136f Add printing the LC_SUB_LIBRARY load command with llvm-objdump’s -private-headers.
llvm-svn: 224607
2014-12-19 19:48:16 +00:00
Colin LeMahieu
b6c1e97753 [Hexagon] Adding xtype shift instructions.
llvm-svn: 224604
2014-12-19 19:34:50 +00:00
Colin LeMahieu
16013f08b8 [Hexagon] Adding transfers to and from control registers.
llvm-svn: 224599
2014-12-19 19:06:32 +00:00