RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-25 14:02:52 +02:00
Code Issues Projects Releases Wiki Activity
137,655 Commits 4 Branches 5 Tags 704 MiB
cb71dd00ee
Commit Graph

4 Commits

Author SHA1 Message Date
Tim Northover
99fc73cc8c GlobalISel: omit braces on MachineInstr types when there's only one. 
Tidies up the representation a bit in the common case.

llvm-svn: 276772
 2016-07-26 17:28:01 +00:00
Tim Northover
4c332c49f1 GlobalISel: allow multiple types on MachineInstrs. 
llvm-svn: 276481
 2016-07-22 22:13:36 +00:00
Tim Northover
aebb01e004 GlobalISel: implement low-level type with just size & vector lanes. 
This should be all the low-level instruction selection needs to determine how
to implement an operation, with the remaining context taken from the opcode
(e.g. G_ADD vs G_FADD) or other flags not based on type (e.g. fast-math).

llvm-svn: 276158
 2016-07-20 19:09:30 +00:00
Tom Stellard
383448325b AMDGPU: Add skeleton GlobalIsel implementation 
Summary:
This adds the necessary target code to be able to run the ir translator.
Lowering function arguments and returns is a nop and there is no support
for RegBankSelect.

Reviewers: arsenm, qcolombet

Subscribers: arsenm, joker.eph, vkalintiris, llvm-commits

Differential Revision: http://reviews.llvm.org/D19077

llvm-svn: 266356
 2016-04-14 19:09:28 +00:00