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Commit Graph

193043 Commits

Author SHA1 Message Date
James Henderson
cd41ba8d27 [DebugInfo] Add check for .debug_line minimum_instruction_length of 0
If the minimum_instruction_length of a debug line program is 0, no
address advancing via special opcodes, DW_LNS_const_add_pc, and
DW_LNS_advance_pc can occur, since the minimum_instruction_length is
used in a multiplication. This patch adds a warning reporting when this
issue occurs.

Reviewed by: probinson

Differential Revision: https://reviews.llvm.org/D75189
2020-03-09 12:59:44 +00:00
James Henderson
eff38d6af0 [DebugInfo] Prevent crash when .debug_line line_range is zero
The line_range value of a debug line program header is used in divisions
related to special opcodes and DW_LNS_const_add_pc opcodes. As such, a
value of 0 cannot be used. This change introduces a new warning, if such
a situation is identified, and does not perform the relevant
calculations.

Reviewed by: probinson, aprantl

Differential Revision: https://reviews.llvm.org/D43470
2020-03-09 12:59:43 +00:00
James Henderson
14ae577b3f [DebugInfo] Report unsupported maximum_operations_per_instruction values
This patch adds a check which reports an unsupported value of the
maximum_operations_per_instruction field in a debug line table header.
This is reported once per line table, at most, and only if the tablet
would otherwise need to use it (i.e. never for tables with version 3 or
less, or for tables which don't use DW_LNS_const_add_pc or special
opcodes). Unsupported values are currently any apart from 1.

Reviewed by: probinson, MaskRay

Differential Revision: https://reviews.llvm.org/D74819
2020-03-09 12:59:43 +00:00
James Henderson
7505a1b388 [NFC][DebugInfo] Refactor address advancing operations to share code
This change is a preparatory change for subsequent commits.

Reviewed by: probinson

Differential Revision: https://reviews.llvm.org/D75188
2020-03-09 12:59:43 +00:00
Alex Cameron
5afbf35b3f [XRay] Sanitize DOT labels in graph output
Summary:
Bugzilla: https://bugs.llvm.org/show_bug.cgi?id=39701

This patch is to convert certain characters to their XML escape sequences when generating labels for a DOT graph.

I had trouble reproducing the exact issue described on the tracker. I ran `llvm-xray graph` on a log from a test program that included function templates but wasn't able to get the `dot` tool to complain about the `<` and `>` characters. The documentation also suggests that the escape sequences should only be necessary when using HTML string labels which XRay doesn't use (`label=<...>` as opposed to `label="..."`). Perhaps newer versions of Graphviz silently handle this in the case of quoted-string labels.

In any case, the generated labels still look correct after this patch and should also fix the reporter's issue.

I was a bit unsure how to add a test for this since the existing tests seem to only care about `func-id` rather than giving an actual name. If you could give me a hint on the best way to go about this, that'd be much appreciated!

Reviewers: dberris

Reviewed By: dberris

Subscribers: lebedev.ri, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69461
2020-03-09 12:05:57 +00:00
evgeny
dcf4590f35 [WPD] Provide a way to prevent functions from being devirtualized
Differential revision: https://reviews.llvm.org/D75617
2020-03-09 14:05:15 +03:00
Djordje Todorovic
df8a19e738 [CallSiteInfo] Enable the call site info only for -g + optimizations
Emit call site info only in the case of '-g' + 'O>0' level.

Differential Revision: https://reviews.llvm.org/D75175
2020-03-09 12:12:44 +01:00
KAWASHIMA Takahiro
9cc8f671d4 [AArch64] Add support for Fujitsu A64FX
A64FX is an Armv8.2-A CPU used in FUJITSU Supercomputer
PRIMEHPC FX1000, PRIMEHPC FX700, and supercomputer Fugaku.

https://www.fujitsu.com/global/products/computing/servers/supercomputer/specifications/

Differential Revision: https://reviews.llvm.org/D75594
2020-03-09 19:15:09 +09:00
Clement Courbet
728ae1c6fb [ExpandMemCmp] Properly constant-fold all compares.
Summary:
This gets rid of duplicated code and diverging behaviour w.r.t.
constants.
Fixes PR45086.

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D75519
2020-03-09 10:40:52 +01:00
Clement Courbet
78f1c8ce60 [ExpandMemCmp] Properly constant-fold all compares.
Summary:
This gets rid of duplicated code and diverging behaviour w.r.t.
constants.
Fixes PR45086.

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D75519
2020-03-09 09:10:34 +01:00
Hideto Ueno
d0411927a9 [Attributor] Deduction based on path exploration
This patch introduces the propagation of known information based on path exploration.
For example,
```
int u(int c, int *p){
  if(c) {
     return *p;
  } else {
     return *p + 1;
  }
}
```
An argument `p` is dereferenced whatever c's value is.

For an instruction `CtxI`, we accumulate branch instructions in the must-be-executed-context of `CtxI` and then, we take the conjunction of the successors' known state.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D65593
2020-03-09 14:29:26 +09:00
Craig Topper
04fea0f103 [X86] Remove isel patterns that matched vXi16 X86VBroadcast with i8->i16 aextload input.
This was selecting VBROADCASTW which turned the 8-bit load into
a 16-bit load if it happened to be 2 byte aligned.

I have a plan to fix the regression with a follow up patch
which I'll post shortly.
2020-03-08 19:16:24 -07:00
David Green
880657dd53 [ARM] MVE VMULL tests. NFC 2020-03-08 14:39:08 +00:00
Sanjay Patel
2a676af4c8 [VectorCombine] fold extract-extract-op with different extraction indexes
opcode (extelt V0, Ext0), (ext V1, Ext1) --> extelt (opcode (splat V0, Ext0), V1), Ext1

The first part of this patch generalizes the cost calculation to accept
different extraction indexes. The second part creates a shuffle+extract
before feeding into the existing code to create a vector op+extract.

The patch conservatively uses "TargetTransformInfo::SK_PermuteSingleSrc"
rather than "TargetTransformInfo::SK_Broadcast" (splat specifically
from element 0) because we do not have a more general "SK_Splat"
currently. That does not affect any of the current regression tests,
but we might be able to find some cost model target specialization where
that comes into play.

I suspect that we can expose some missing x86 horizontal op codegen with
this transform, so I'm speculatively adding a debug flag to disable the
binop variant of this transform to allow easier testing.

The test changes show that we're sensitive to cost model diffs (as we
should be), so that means that patches like D74976
should have better coverage.

Differential Revision: https://reviews.llvm.org/D75689
2020-03-08 09:57:55 -04:00
Sanjay Patel
ec5de0c81d [VectorCombine] add tests for wider vectors; NFC 2020-03-08 09:33:07 -04:00
Kang Zhang
3248651cb7 [NFC][PowerPC] Order the MTSTR/MFSPR InstAlias definetion by SPR
Summary:
This NFC patch is only modify the position of MTSTR/MFSPR InstAlias
definition. So it will be easy to read.
2020-03-08 11:58:53 +00:00
LLVM GN Syncbot
599dfc4b73 [gn build] Port 57c964aaa76 2020-03-08 11:50:36 +00:00
Tyker
6cceba3068 [AssumeBundles] Move to IR so it can be used by Analysis
Summary:
Assume bundles need to be usable by Analysis and Transforms/Utils isn't.
so this commit moves utilities to deal with asusme bundles to IR.

Reviewers: jdoerfert

Reviewed By: jdoerfert

Subscribers: mgorny, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D75618
2020-03-08 12:21:50 +01:00
Tyker
1f48436556 [AssumeBundles] Add API to query a bundles from a use
Summary: Finding what information is know about a value from a use is generally useful and can be done quickly.

Reviewers: jdoerfert

Reviewed By: jdoerfert

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D75616
2020-03-08 12:04:23 +01:00
Craig Topper
c5b36c0e65 [X86] Add DAG combine to turn (vzext_movl (vbroadcast_load)) -> vzext_load.
If we're zeroing the other elements then we don't need the broadcast.
2020-03-08 00:35:40 -08:00
Kang Zhang
bf96dd7026 Revert "[NFC][PowerPC] Remove the repeated definition for some InstAlias of mtspr/mfspr"
This reverts commit 46126a30f268a54dc68a40ca07556cf8aca5edbc.
Some test cases failed.
2020-03-08 06:32:12 +00:00
Kang Zhang
9f9f25a82a [NFC][PowerPC] Remove the repeated definition for some InstAlias of mtspr/mfspr
Summary:
Below InstAlias have been redeclaration, this patch is to remove them.
mtdec/mfdec   mtsdr1/mfsdr1     mtsrr0/mfsrr0    mtsrr1/mfsrr1
2020-03-08 06:02:55 +00:00
Craig Topper
f8f9960480 [X86] Add DAG combine to replace vXi64 vzext_movl+scalar_to_vector with vYi32 vzext_movl+scalar_to_vector if the upper 32 bits of the scalar are zero.
We can just use a 32-bit copy and zero in the SSE domain when we
zero the upper bits.

Remove an isel pattern that becomes dead with this.
2020-03-07 16:14:26 -08:00
Craig Topper
cddfb95335 [X86] Add DAG combines to enable removing of movddup/vbroadcast + simple_load isel patterns. 2020-03-07 15:22:02 -08:00
Craig Topper
482b803237 [X86] Add a DAG combine to turn vbroadcast(vzload X) -> vbroadcast_load
Remove now unneeded isel patterns.
2020-03-07 15:22:02 -08:00
kpdev
f7695271bc [NFC][Test commit] Remove redundant point in docs 2020-03-07 10:30:42 +03:00
Craig Topper
0f8eb35c13 [X86] Use MVT instead of EVT in a couple shuffle lowering functions. 2020-03-07 09:50:53 -08:00
Nikita Popov
0394d877a8 [InstCombine] Fix known bits handling in SimplifyDemandedUseBits
Fixes a regression from D75801. SimplifyDemandedUseBits() is also
supposed to compute the known bits (of the demanded subset) of the
instruction. For unknown instructions it does so by directly calling
computeKnownBits(). For known instructions it will compute known
bits itself. However, for instructions where only some cases are
handled directly (e.g. a constant shift amount) the known bits
invocation for the unhandled case is sometimes missing. This patch
adds the missing calls and thus removes the main discrepancy with
ExpensiveCombines mode.

Differential Revision: https://reviews.llvm.org/D75804
2020-03-07 18:16:41 +01:00
Matt Arsenault
d127f8eefb Assume ieee behavior without denormal-fp-math attribute 2020-03-07 12:10:56 -05:00
Nikita Popov
9cf5fbac61 [InstCombine] Regenerate test checks; NFC 2020-03-07 17:58:33 +01:00
Nikita Popov
fdc91198f1 [InstSimplify] Add tests for "returned" attribute; NFC 2020-03-07 17:17:21 +01:00
Nikita Popov
e37fe0311a [InstCombine] Add additional known bits folding tests; NFC 2020-03-07 17:17:03 +01:00
Nikita Popov
57a74f64e3 [InstCombine] Highlight tests using expensive combines; NFC 2020-03-07 17:16:47 +01:00
Sanjay Patel
ce0f3e8557 [InstCombine] regenerate complete test checks; NFC 2020-03-07 10:20:38 -05:00
Sanjay Patel
f0de4cc6f2 [InstCombine] add test for gep (select),... (PR45084); NFC 2020-03-07 10:00:31 -05:00
Sourabh Singh Tomar
6b31d13fe1 [DebugInfo]: Added DWARFv5 macro header flags and corresponding helper
functions.
2020-03-07 17:53:01 +05:30
Stefanos Baziotis
18edbe50e4 [Attributor] Fold terminators before changing instructions to unreachable
It is possible that an instruction to be changed to unreachable is
in the same block with a terminator that can be constant-folded.
In this case, as of now, the instruction will be changed to
unreachable before the terminator is folded. But, then the
whole BB becomes invalidated and so when we go ahead to fold
the terminator, we trap.

Change the order of these two.

Differential Revision: https://reviews.llvm.org/D75780
2020-03-07 12:38:44 +02:00
Amara Emerson
270c4cc3bd Revert "Revert "[GlobalISel][Localizer] Enable intra-block localization of already-local uses.""
This reverts commit 5583c2f2fba5be1df60f00cbc34a5098b5a49909.

The lldb bot failure was a test that was fragile and sensitive to irrelevant
changes in instruction ordering. Re-committing this as the test should have
been skipped for AArch64 now.

Differential Revision: https://reviews.llvm.org/D75555
2020-03-06 21:35:08 -08:00
Hal Finkel
027c7f68e8 Add the CodeReview Documentation to GettingInvolved TOC 2020-03-07 04:55:46 +00:00
Hal Finkel
7fc69daf0c High-Level Code-Review Documentation Update
This is an update to the documentation of our community code-review process.
Based on the RFC: High-Level Code-Review Documentation Update
(http://lists.llvm.org/pipermail/llvm-dev/2019-November/136808.html).

In this patch, I've pulled out the documentation into a separate file, and
broken it into a number of subsections. This is, of course, just one further
step in better documenting our community processes. I expect we'll continue to
improve this over time. Thank you to everyone who provided feedback!

Differential Revision: https://reviews.llvm.org/D71916
2020-03-07 04:20:18 +00:00
Nico Weber
4e4163852d [gn build] copy compiler-rt headers to clang include dir on all platforms 2020-03-06 21:55:56 -05:00
Greg Clayton
30d1a6646f Fix a copy and paste error that would cause a crash.
Summary: The wrong variable was being checked for an error, which mean a llvm::Error went unchecked and crashes dsymutil. Discovered this when trying to feed an ELF file to "dsymutil --update" and running into the crash.

Reviewers: aprantl, JDevlieghere

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D75777
2020-03-06 18:07:36 -08:00
Andrew Monshizadeh
cc7164597b Extend TimeTrace to LLVM's new pass manager
With the addition of the LLD time tracing it made sense to include coverage
for LLVM's various passes. Doing so ensures that ThinLTO is also covered
with a time trace.

Before:
{F11333974}

After:
{F11333928}

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D74516
2020-03-06 14:45:19 -08:00
Andrew Monshizadeh
d85c60126a Refactor TimeProfiler write methods (NFC)
Added a write method for TimeTrace that takes two strings representing
file names. The first is any file name that may have been provided by the
user via `time-trace-file` flag, and the second is a fallback that should
be configured by the caller. This method makes it cleaner to write the
trace output because there is no longer a need to check file names at the
caller and simplifies future TimeTrace usages.

Reviewed By: modocache

Differential Revision: https://reviews.llvm.org/D74514
2020-03-06 14:34:56 -08:00
Shivam Gupta
7f5ff28640 Correct the Bjarne Stroustrup's C++ Page link
Summary: Bjarne Stroustrup's C++ Page link pointing to wrong AT&T page.

Reviewers: jyknight, sanjoy, silvas, hubert.reinterpretcast

Reviewed By: hubert.reinterpretcast

Subscribers: hubert.reinterpretcast, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D75709
2020-03-06 16:59:50 -05:00
Fangrui Song
2f8afd481f [gold][test] Fix tests after D75713 and D74749 2020-03-06 13:38:04 -08:00
Reid Kleckner
c6d9f2883f Avoid emitting unreachable SP adjustments after throw
In 172eee9c, we tried to avoid these by modelling the callee as
internally resetting the stack pointer.

However, for the majority of functions with reserved stack frames, this
would lead LLVM to emit extra SP adjustments to undo the callee's
internal adjustment. This lead us to fix the problem further on down the
pipeline in eliminateCallFramePseudoInstr. In 5b79e603d3b7a2994, I added
use a heuristic to try to detect when the adjustment would be
unreachable.

This heuristic is imperfect, and when exception handling is involved, it
fails to fire. The new test is an example of this. Simply throwing an
exception with an active cleanup emits dead SP adjustments after the
throw. Not only are they dead, but if they were executed, they would be
incorrect, so they are confusing.

This change essentially reverts 172eee9c and makes the 5b79e603d3b7a2994
heuristic responsible for preventing unreachable stack adjustments. This
means we may emit unreachable stack adjustments for functions using EH
with unreserved call frames, but that is not very many these days. Back
in 2016 when this change was added, we were focused on 32-bit, which we
observed to have fewer reserved frames.

Fixes PR45064

Reviewed By: hans

Differential Revision: https://reviews.llvm.org/D75712
2020-03-06 13:33:45 -08:00
Anna Thomas
3ed40701a3 [RS4GC] Handle uses of extractelement for conversion from vector to scalar base
As mentioned in the comments, extractelement is special
since we actually want a scalar base for that element we extracted from
the vector (i.e. not a vector base).
This same logic should apply to uses of the extractelement such as phis
and selects which have the same BDV as the extractelement.
Howeber, for these uses we conservatively mark the BDV state as
conflict, since setting the EE's new base BDV does not always dominate
these uses.

Added testcase showcases the problem where the BDV identification chokes
on the incorrect cast from vector to scalar for the phi use of
extractelement.

Tests-Run: make check, internal fuzzer testing

Reviewers: reames, skatkov, dantrushin
Reviewed-By: dantrushin

Differential Revision: https://reviews.llvm.org/D75704
2020-03-06 16:28:49 -05:00
Roman Lebedev
7c5b5c8fe7 [InstComine] Forego of one-use check in (X - (X & Y)) --> (X & ~Y) if Y is a constant
Summary:
This is potentially more friendly for further optimizations,
analysies, e.g.: https://godbolt.org/z/G24anE

This resolves phase-ordering bug that was introduced
in D75145 for https://godbolt.org/z/2gBwF2
https://godbolt.org/z/XvgSua

Reviewers: spatel, nikic, dmgreen, xbolva00

Reviewed By: nikic, xbolva00

Subscribers: hiraditya, zzheng, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D75757
2020-03-06 21:39:07 +03:00
Craig Topper
4ecd36110b [X86] Cleanup patterns and ins for VCVTNEPS2BF16.
There was a noop bitconvert in the load pattern. While there
also make all the sources refer to src_v.RC even though its the
same as _.RC, but its consistent.
2020-03-06 10:15:37 -08:00