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127 Commits

Author SHA1 Message Date
Matheus Almeida
394228ce3f [mips][msa] Direct Object Emission for the majority of the ELM instructions. 
llvm-svn: 192449
 2013-10-11 13:39:49 +00:00
Matheus Almeida
4a18a3f38a [mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction. 
INSERT is the first type of MSA instruction that requires a change to the way MSA registers are parsed. 
This happens because MSA registers may be suffixed by an index in the form of an immediate or a
 general purpose register. The changes to parseMSARegs reflect that requirement.

llvm-svn: 192447
 2013-10-11 13:29:36 +00:00
Daniel Sanders
3649e05b17 [mips][msa] Added support for matching maddv.[bhwd], and msubv.[bhwd] from normal IR (i.e. not intrinsics) 
llvm-svn: 192438
 2013-10-11 10:50:42 +00:00
Daniel Sanders
9bec7b823b [mips][msa] Added support for matching fmsub.[wd] from normal IR (i.e. not intrinsics) 
llvm-svn: 192435
 2013-10-11 10:27:32 +00:00
Daniel Sanders
253e018134 [mips][msa] Added support for matching fmadd.[wd] from normal IR (i.e. not intrinsics) 
llvm-svn: 192430
 2013-10-11 10:14:25 +00:00
Daniel Sanders
4971ec128b [mips][msa] Added support for matching ffint_[us].[wd], and ftrunc_[us].[wd] from normal IR (i.e. not intrinsics) 
llvm-svn: 192429
 2013-10-11 10:00:06 +00:00
Daniel Sanders
6ffe6fc99c [mips][msa] Added support for matching mod_[us] from normal IR (i.e. not intrinsics) 
llvm-svn: 191737
 2013-10-01 10:22:35 +00:00
Jack Carter
87696d33e7 [mips][msa] Direct Object Emission for I8 instructions. 
This patch adds Direct Object Emission support for I8 instructions: andi.b, bmnzi.b, bmzi.b, bseli.b, nori.b, ori.b, shf.{b,h,w} and xori.b.


Patch by Matheus Almeida

llvm-svn: 191688
 2013-09-30 18:05:18 +00:00
Jack Carter
ef8714ee72 [mips][msa] Direct Object Emission for I5 instructions. 
This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}.


Patch by Matheus Almeida

llvm-svn: 191687
 2013-09-30 17:58:07 +00:00
Jack Carter
edd6f0149e [mips][msa] Direct Object Emission for 2R instructions. 
This patch adds Direct Object Emission support for 2R instructions: nloc.{b,h,w}, nlzc.{b,h,w}, pcnt.{b,w,d}.  


Patch by Matheus Almeida

llvm-svn: 191685
 2013-09-30 17:52:33 +00:00
Jack Carter
0d832949ac [PATCH 1/4] [mips][msa] Source register of FILL instructions is GPR 
and not an MSA register

Patch by Matheus Almeida

llvm-svn: 191684
 2013-09-30 17:43:04 +00:00
Daniel Sanders
fccbe04cbf [mips][msa] Rename arguments to MSA_INSERT_DESC_BASE to better match their expected values. 
No functional change.

llvm-svn: 191517
 2013-09-27 12:45:08 +00:00
Daniel Sanders
8c83ddcdd2 [mips][msa] Implemented insert_vector_elt for v4f32 and v2f64. 
For v4f32 and v2f64, INSERT_VECTOR_ELT is matched by a pseudo-insn which is
later expanded to appropriate insve.[wd] insns.

llvm-svn: 191515
 2013-09-27 12:31:32 +00:00
Daniel Sanders
0bb1b5a37f [mips][msa] Implemented extract_vector_elt for v4f32 or v2f64 
For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may
be expanded to subregister copies and/or instructions as appropriate.

llvm-svn: 191514
 2013-09-27 12:17:32 +00:00
Daniel Sanders
8e7e5fd076 [mips][msa] Added support for matching splati from normal IR (i.e. not intrinsics) 
Updated some of the vshf since they (correctly) emit splati's now

llvm-svn: 191511
 2013-09-27 11:48:57 +00:00
Jack Carter
114828ff6a [mips][msa] Direct Object Emission for 3RF instructions. 
Patch by Matheus Almeida

llvm-svn: 191461
 2013-09-26 21:31:43 +00:00
Jack Carter
d8f36be034 [mips][msa] Updates encoding of 3RF instructions to match the latest revision of the MSA spec (1.06). 
This does not affect any of the existing output.

Patch by Matheus Almeida

llvm-svn: 191460
 2013-09-26 21:18:57 +00:00
Jack Carter
8c179a17e8 [mips][msa] Direct Object Emission for 3R instructions. 
This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class.
 
Patch by Matheus Almeida

llvm-svn: 191415
 2013-09-26 00:09:46 +00:00
Jack Carter
dc0125898e [mips][msa] Updates encoding of 3R instructions to match the latest revision of the MSA spec (1.06). 
Internal changes only.
 
Patch by Matheus Almeida

llvm-svn: 191414
 2013-09-26 00:02:44 +00:00
Jack Carter
1acc13e85e [mips][msa] Direct Object Emission for 2RF instructions. 
Patch by Matheus Almeida

llvm-svn: 191413
 2013-09-25 23:56:25 +00:00
Jack Carter
21047e3a83 [mips][msa] Direct Object Emission support for the MSA instruction set. 
In more detail, this patch adds the ability to parse, encode and decode MSA registers ($w0-$w31). The format of 2RF instructions (MipsMSAInstrFormat.td) was updated so that we could attach a test case to this patch i.e., the test case parses, encodes and decodes 2 MSA instructions. Following patches will add the remainder of the instructions.

Note that DecodeMSA128BRegisterClass is missing from MipsDisassembler.td because it's not yet required at this stage and having it would cause a compiler warning (unused function).

Patch by Matheus Almeida

llvm-svn: 191412
 2013-09-25 23:50:44 +00:00
Jack Carter
c6a3b6cb88 [mips][msa] Updates encoding of 2RF instructions to match the latest revision of the MSA spec (1.06). 
This only changes internal encodings and doesn't affect output.


Patch by Matheus Almeida

llvm-svn: 191411
 2013-09-25 23:42:03 +00:00
Daniel Sanders
d110591231 [mips][msa] Added support for matching pckev, and pckod from normal IR (i.e. not intrinsics) 
llvm-svn: 191306
 2013-09-24 14:53:25 +00:00
Daniel Sanders
48059bf5ef [mips][msa] Added support for matching ilv[lr], ilvod, and ilvev from normal IR (i.e. not intrinsics) 
llvm-svn: 191304
 2013-09-24 14:36:12 +00:00
Daniel Sanders
db41b542e8 [mips][msa] Added support for matching shf from normal IR (i.e. not intrinsics) 
llvm-svn: 191302
 2013-09-24 14:20:00 +00:00
Daniel Sanders
7c64721346 [mips][msa] Added support for matching vshf from normal IR (i.e. not intrinsics) 
llvm-svn: 191301
 2013-09-24 14:02:15 +00:00
Daniel Sanders
e154d03143 [mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. 
Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover
bitcasted as well as normal vectors. However, it doesn't seem to be possible to
match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of
immediates, it should be possible to use ldi.b to load v2i64) using TableGen so
ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp

This made the majority of the constant splat BUILD_VECTOR lowering redundant.
The only transformation remaining for constant splats is when an (up-to) 32-bit
constant splat is possible but the value does not fit into a 10-bit signed
integer. In this case, the BUILD_VECTOR is transformed into a bitcasted
BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32
register (which is initialized using the usual lui/addui sequence).

There are no additional tests since this is a re-implementation of previous
functionality. The change is intended to make it easier to implement some of
the upcoming instruction selection patches since they can rely on existing
support for BUILD_VECTOR's in the DAGCombiner.

compare_float.ll changed slightly because a BITCAST is no longer
introduced during legalization.

llvm-svn: 191299
 2013-09-24 13:33:07 +00:00
Daniel Sanders
d201758a30 [mips][msa] Added partial support for matching fmax_a from normal IR (i.e. not intrinsics) 
This covers the case where fmax_a can be used to implement ISD::FABS.

llvm-svn: 191296
 2013-09-24 13:02:08 +00:00
Daniel Sanders
d3d61d6b42 [mips][msa] Line wrapping. 
No functional change.

llvm-svn: 191295
 2013-09-24 12:45:36 +00:00
Daniel Sanders
fe71effbbd [mips][msa] Added support for matching andi, ori, nori, and xori from normal IR (i.e. not intrinsics) 
llvm-svn: 191293
 2013-09-24 12:32:47 +00:00
Daniel Sanders
f05ed8bd9a [mips][msa] Added support for matching max, maxi, min, mini from normal IR (i.e. not intrinsics) 
llvm-svn: 191291
 2013-09-24 12:18:31 +00:00
Daniel Sanders
0167ec55f4 [mips][msa] Added support for matching bsel and bseli from normal IR (i.e. not intrinsics) 
This required correcting the definition of the bsel and bseli intrinsics.

llvm-svn: 191290
 2013-09-24 12:04:44 +00:00
Daniel Sanders
9a3de1f604 [mips][msa] Added support for matching comparisons from normal IR (i.e. not intrinsics) 
MIPS SelectionDAG changes:
* Added VCEQ, VCL[ET]_[SU] nodes to represent vector comparisons that produce a bitmask.

llvm-svn: 191286
 2013-09-24 10:46:19 +00:00
Daniel Sanders
362149b5a7 [mips][msa] Added support for matching slli, srai, and srli from normal IR (i.e. not intrinsics) 
llvm-svn: 191285
 2013-09-24 10:28:18 +00:00
Daniel Sanders
ced4e4005c [mips][msa] Added support for matching addvi, and subvi from normal IR (i.e. not intrinsics) 
llvm-svn: 191203
 2013-09-23 14:29:55 +00:00
Daniel Sanders
34cb8f3e4d [mips][msa] Added support for matching insert and copy from normal IR (i.e. not intrinsics) 
Changes to MIPS SelectionDAG:
* Added nodes VEXTRACT_[SZ]EXT_ELT to represent extract and extend in a single
  operation and implemented the DAG combines necessary to fold sign/zero
  extends into the extract.

llvm-svn: 191199
 2013-09-23 14:03:12 +00:00
Daniel Sanders
d1df1263eb [mips][msa] Added support for matching pcnt from normal IR (i.e. not intrinsics) 
llvm-svn: 191198
 2013-09-23 13:40:21 +00:00
Daniel Sanders
7d945d142d [mips][msa] Added support for matching nor from normal IR (i.e. not intrinsics) 
llvm-svn: 191195
 2013-09-23 13:22:24 +00:00
Daniel Sanders
91c78d1d33 [mips][msa] Added support for matching and, or, and xor from normal IR (i.e. not intrinsics) 
llvm-svn: 191194
 2013-09-23 12:57:42 +00:00
Daniel Sanders
d3c403c386 [mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD) 
Note: There's a later patch on my branch that re-implements this to select
build_vector without the custom SelectionDAG nodes. The future patch avoids
the constant-folding problems stemming from the custom node (i.e. it doesn't
need to re-implement all the DAG combines related to BUILD_VECTOR).

Changes to MIPS specific SelectionDAG nodes:
* Added VSPLAT
    This is a special case of BUILD_VECTOR that covers the case the
    BUILD_VECTOR is a splat operation.
* Added VSPLATD
    This is a special case of VSPLAT that handles the cases when v2i64 is legal

llvm-svn: 191191
 2013-09-23 12:02:46 +00:00
Daniel Sanders
e3f2e5de18 [mips][msa] Added support for matching mulv, nlzc, sll, sra, srl, and subv from normal IR (i.e. not intrinsics) 
llvm-svn: 190518
 2013-09-11 11:58:30 +00:00
Daniel Sanders
96466ff8b4 [mips][msa] Added support for matching fadd, fdiv, flog2, fmul, frint, fsqrt, and fsub from normal IR (i.e. not intrinsics) 
llvm-svn: 190512
 2013-09-11 10:51:30 +00:00
Daniel Sanders
a52c7f09dc [mips][msa] Added support for matching div_[su] from normal IR (i.e. not intrinsics) 
llvm-svn: 190509
 2013-09-11 10:38:58 +00:00
Daniel Sanders
f68b00e629 [mips][msa] Added support for matching addv from normal IR (i.e. not intrinsics) 
The corresponding intrinsic is now lowered into equivalent IR (ISD::ADD) before instruction selection.

llvm-svn: 190507
 2013-09-11 10:28:16 +00:00
Daniel Sanders
534d28aa11 [mips][msa] Corrected the definition of the dotp_[su].[hwd] intrinsics 
The elements of the operands should be half the width of the elements of
the result.

llvm-svn: 190505
 2013-09-11 09:59:17 +00:00
Daniel Sanders
32227b7995 [mips][msa] Removed unsupported dot product instructions (dotp_[su].b) 
The dotp_[su].b instructions never existed in any revision of the MSA spec.

llvm-svn: 190398
 2013-09-10 09:51:43 +00:00
Akira Hatanaka
c11e303acd [mips] Use uimm5 and uimm6 instead of shamt and imm, if the immediate has to fit 
into a 5-bit or 6-bit field.

llvm-svn: 190226
 2013-09-07 00:02:02 +00:00
Daniel Sanders
10a7da8f65 [mips][msa] Indentation 
llvm-svn: 190156
 2013-09-06 13:25:06 +00:00
Daniel Sanders
11008ea159 [mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance 
Tested with 'llvm-tblgen -print-records' which outputs identical records before
and after this patch.

llvm-svn: 190155
 2013-09-06 13:15:05 +00:00
Daniel Sanders
22d0137a75 [mips][msa] Made the operand register sets optional for the VEC formats 
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190153
 2013-09-06 13:01:47 +00:00
Daniel Sanders
0eb9e53280 [mips][msa] Made the operand register sets optional for the ELM_INSVE formats 
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190151
 2013-09-06 12:50:52 +00:00
Daniel Sanders
cb68899283 [mips][msa] Made the operand register sets optional for the 3RF_4RF format 
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190150
 2013-09-06 12:44:13 +00:00
Daniel Sanders
d9577fe859 [mips][msa] Made the operand register sets optional for the 3RF formats 
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190146
 2013-09-06 12:32:57 +00:00
Daniel Sanders
6089833291 [mips][msa] Made the operand register sets optional for the 3R_4R format 
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190145
 2013-09-06 12:30:43 +00:00
Daniel Sanders
e8f95344a5 [mips][msa] Made the operand register sets optional for the 2RF format 
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190143
 2013-09-06 12:28:13 +00:00
Daniel Sanders
5e6aa9c0b4 [mips][msa] Made the operand register sets optional for the I8 format 
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190142
 2013-09-06 12:25:47 +00:00
Daniel Sanders
caabc263f0 [mips][msa] Made the operand register sets optional for the I5 and SI5 formats 
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190141
 2013-09-06 12:23:19 +00:00
Daniel Sanders
e90f0ba299 [mips][msa] Made the operand register sets optional for the BIT_[BHWD] formats 
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190140
 2013-09-06 12:10:24 +00:00
Daniel Sanders
66131ccd3e [mips][msa] Sorted MSA_BIT_[BHWD]_DESC_BASE into ascending order of element size 
No functional change

llvm-svn: 190134
 2013-09-06 11:01:38 +00:00
Daniel Sanders
d571ce1dd4 [mips][msa] Made the operand register sets optional for the 3R format 
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190133
 2013-09-06 10:59:24 +00:00
Daniel Sanders
87992178d5 [mips][msa] Made the InstrItinClass argument optional since it is always NoItinerary at the moment. 
No functional change

llvm-svn: 190131
 2013-09-06 10:55:15 +00:00
Daniel Sanders
7d6b0c31fc [mips][msa] Added bnz.df, bnz.v, bz.df, and bz.v 
These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes,
are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as
a branch/mov sequence to evaluate to 0 or 1.

Note: The resulting code is sub-optimal since it doesnt seem to be possible
to feed the result of an intrinsic directly into a brcond. At the moment
it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily
evaluates the boolean twice.

llvm-svn: 189478
 2013-08-28 12:14:50 +00:00
Daniel Sanders
86a3b104b1 [mips][msa] Added load/store intrinsics. 
llvm-svn: 189476
 2013-08-28 12:04:29 +00:00
Daniel Sanders
6583601738 [mips][msa] Added move.v 
llvm-svn: 189471
 2013-08-28 10:44:47 +00:00
Daniel Sanders
21800e80c1 [mips][msa] Added cfcmsa, and ctcmsa 
The MSA control registers have been added as reserved registers,
and are only used via ISD::Copy(To|From)Reg. The intrinsics are lowered
into these nodes.

llvm-svn: 189468
 2013-08-28 10:26:24 +00:00
Daniel Sanders
3740f20366 [mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri 
llvm-svn: 189467
 2013-08-28 10:12:09 +00:00
Daniel Sanders
b2c1c16a0a [mips][msa] Added bitconverts for vector types for big and little-endian 
llvm-svn: 189330
 2013-08-27 09:40:30 +00:00
Daniel Sanders
c6286de5e8 [mips][msa] Split MSA128 regset into size-specific sets containing the same registers. 
llvm-svn: 189095
 2013-08-23 10:10:13 +00:00
Daniel Sanders
30561c36b8 [mips][msa] Removed fcge, fcgt, fsge, fsgt 
These instructions were present in a draft spec but were removed before
publication.

llvm-svn: 188782
 2013-08-20 09:41:47 +00:00
Daniel Sanders
91c40d80de [mips][msa] Added insve 
llvm-svn: 188777
 2013-08-20 09:22:54 +00:00
Daniel Sanders
15341e9a12 [mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v 
llvm-svn: 188767
 2013-08-20 08:38:21 +00:00
Daniel Sanders
ee0e14ab3f Reverted test commit (r188556) 
llvm-svn: 188557
 2013-08-16 15:27:12 +00:00
Daniel Sanders
aac10b8a53 Test commit. Just a blank line 
llvm-svn: 188556
 2013-08-16 15:26:36 +00:00
Jack Carter
2c2f78cead [Mips][msa] Added the simple builtins (madd_q to xori) 
Includes:
madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su],
msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev,
pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al],
sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori

Patch by Daniel Sanders

llvm-svn: 188460
 2013-08-15 14:22:07 +00:00
Jack Carter
8798c3bae2 [Mips][msa] Added the simple builtins (fadd to ftq) 
Includes:
fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2,
fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin,
fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt,
fsne, fsqr, fsub, ftint_s, ftq

Patch by Daniel Sanders

llvm-svn: 188458
 2013-08-15 13:45:36 +00:00
Jack Carter
80890657b3 [Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) 
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi

Patch by Daniel Sanders

llvm-svn: 188457
 2013-08-15 12:24:57 +00:00
Jack Carter
da7e928e92 [Mips][msa] Added initial MSA support. 
* msa SubtargetFeature
* registers
* ld.[bhwd], and st.[bhwd] instructions

Does not correctly prohibit use of both 32-bit FPU registers and MSA together.

Patch by Daniel Sanders

llvm-svn: 188313
 2013-08-13 20:54:07 +00:00