Venkatraman Govindaraju
34b3409b1a
[Sparc] Add trap on integer condition codes (Ticc) instructions to Sparc backend.
...
llvm-svn: 202670
2014-03-02 23:39:07 +00:00
Venkatraman Govindaraju
caf11daede
[SparcV9] Adds support for branch on integer register instructions (BPr) and conditional moves on integer register (MOVr/FMOVr).
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llvm-svn: 202628
2014-03-02 09:46:56 +00:00
Venkatraman Govindaraju
b02c5bdb65
[Sparc] Make floating point branch instruction formats to accept %fcc0-%fcc1 conditional registers as input.
...
No functionality change.
llvm-svn: 202614
2014-03-02 04:43:45 +00:00
Venkatraman Govindaraju
6aea38dc6d
[Sparc] Add support for parsing fcmp with %fcc registers.
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llvm-svn: 202610
2014-03-02 03:39:39 +00:00
Venkatraman Govindaraju
1c2ec775cb
[SparcV9] Add support for parsing branch instructions with prediction.
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llvm-svn: 202602
2014-03-01 22:03:07 +00:00
Venkatraman Govindaraju
44a4d4b894
[Sparc] Add support for parsing annulled branch instructions.
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llvm-svn: 202599
2014-03-01 20:08:48 +00:00
Venkatraman Govindaraju
772dbc91ad
[Sparc] Emit correct encoding for atomic instructions. Also, add support for parsing CAS instructions to test the CAS encoding.
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llvm-svn: 200963
2014-02-07 07:34:49 +00:00
Venkatraman Govindaraju
0e7023f897
[SparcV9] Rename operands in some sparc64 instructions so that TableGen can encode them correctly.
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llvm-svn: 198740
2014-01-08 07:47:57 +00:00
Venkatraman Govindaraju
63a6ceb84a
[Sparc] Add initial implementation of disassembler for sparc
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llvm-svn: 198591
2014-01-06 08:08:58 +00:00
Venkatraman Govindaraju
a015f53847
[Sparc] Make SPARC instructions' encoding well defined such that TableGen can automatically generate code emitter.
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llvm-svn: 191168
2013-09-22 09:54:42 +00:00
Venkatraman Govindaraju
71c981302c
[Sparc] Clean up MOVcc instructions so that TableGen can encode them correctly. No functionality change intended.
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llvm-svn: 191167
2013-09-22 09:18:26 +00:00
Venkatraman Govindaraju
953c8fbf21
[Sparc] Clean up branch instructions, so that TableGen can encode branch conditions as well. No functionality change intended.
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llvm-svn: 191166
2013-09-22 08:51:55 +00:00
Venkatraman Govindaraju
a65d380b15
Sparc: No functionality change. Cleanup whitespaces, comment formatting etc.,
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llvm-svn: 183243
2013-06-04 18:33:25 +00:00
Jakob Stoklund Olesen
3b790b7f2e
Use i32 for all SPARC shift amounts, even in 64-bit mode.
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Test case by llvm-stress.
llvm-svn: 179477
2013-04-14 05:48:50 +00:00
Jakob Stoklund Olesen
5ef2195726
Add 64-bit shift instructions.
...
SPARC v9 defines new 64-bit shift instructions. The 32-bit shift right
instructions are still usable as zero and sign extensions.
This adds new F3_Sr and F3_Si instruction formats that probably should
be used for the 32-bit shifts as well. They don't really encode an
simm13 field.
llvm-svn: 178525
2013-04-02 04:09:12 +00:00
Jia Liu
b077b6085d
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
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llvm-svn: 150878
2012-02-18 12:03:15 +00:00
Chris Lattner
ad9a6ccb83
Remove attribution from file headers, per discussion on llvmdev.
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llvm-svn: 45418
2007-12-29 20:36:04 +00:00
Evan Cheng
8312ed6f77
Change instruction description to split OperandList into OutOperandList and
...
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 01:14:50 +00:00
Chris Lattner
fa87f12b85
Use a couple of multiclass patterns to factor some integer ops.
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llvm-svn: 30039
2006-09-01 22:28:02 +00:00
Chris Lattner
834685ef3a
Rename SPARC V8 target to be the LLVM SPARC target.
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llvm-svn: 25985
2006-02-05 05:50:24 +00:00
