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Commit Graph

606 Commits

Author SHA1 Message Date
Owen Anderson
d003a613e7 Teach SelectionDAG to match more calls to libm functions onto existing SDNodes. Mark these nodes as illegal by default, unless the target declares otherwise.
llvm-svn: 146171
2011-12-08 19:32:14 +00:00
Nick Lewycky
7d0d3c2d58 Move global variables in TargetMachine into new TargetOptions class. As an API
change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.

One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.

llvm-svn: 145714
2011-12-02 22:16:29 +00:00
Hal Finkel
77cfe064a7 add basic PPC register-pressure feedback; adjust the vaarg test to match the new register-allocation pattern
llvm-svn: 145065
2011-11-22 16:21:04 +00:00
Jay Foad
7d05fea7f8 Remove some unnecessary includes of PseudoSourceValue.h.
llvm-svn: 144631
2011-11-15 07:24:32 +00:00
Pete Cooper
224434deec Added invariant field to the DAG.getLoad method and changed all calls.
When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses

llvm-svn: 144100
2011-11-08 18:42:53 +00:00
Lang Hames
e8bb71f80d Rename NonScalarIntSafe to something more appropriate.
llvm-svn: 143080
2011-10-26 23:50:43 +00:00
Hal Finkel
f61af0e4b0 Revert change to function alignment b/c existing logic was fine
llvm-svn: 142224
2011-10-17 18:53:03 +00:00
Hal Finkel
f5b7d5ea68 Instructions for Book E PPC should be word aligned, set function alignment to reflect this
llvm-svn: 142194
2011-10-17 17:01:41 +00:00
Hal Finkel
8e97422bd9 Add an implementation of the CanLowerReturn function to the PPC backend
llvm-svn: 141981
2011-10-14 19:51:36 +00:00
Duncan Sands
d1311488fe Add codegen support for vector select (in the IR this means a select
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons.  Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all").  Patch mostly by
Nadav Rotem.

llvm-svn: 139159
2011-09-06 19:07:46 +00:00
Duncan Sands
6939ae53ac Split the init.trampoline intrinsic, which currently combines GCC's
init.trampoline and adjust.trampoline intrinsics, into two intrinsics
like in GCC.  While having one combined intrinsic is tempting, it is
not natural because typically the trampoline initialization needs to
be done in one function, and the result of adjust trampoline is needed
in a different (nested) function.  To get around this llvm-gcc hacks the
nested function lowering code to insert an additional parent variable
holding the adjust.trampoline result that can be accessed from the child
function.  Dragonegg doesn't have the luxury of tweaking GCC code, so it
stored the result of adjust.trampoline in the memory GCC set aside for
the trampoline itself (this is always available in the child function),
and set up some new memory (using an alloca) to hold the trampoline.
Unfortunately this breaks Go which allocates trampoline memory on the
heap and wants to use it even after the parent has exited (!).  Rather
than doing even more hacks to get Go working, it seemed best to just use
two intrinsics like in GCC.  Patch mostly by Sanjoy Das.

llvm-svn: 139140
2011-09-06 13:37:06 +00:00
Roman Divacky
7ac1bc57f7 Set CR1EQ only when lowering vararg floating arguments (not any vararg
arguments as before), unset CR1EQ otherwise.

llvm-svn: 138802
2011-08-30 17:04:16 +00:00
Eli Friedman
6d27cb5e01 Expand ATOMIC_LOAD and ATOMIC_STORE for architectures I don't know well enough to fix properly.
llvm-svn: 138751
2011-08-29 18:23:02 +00:00
Eli Friedman
afd08dcc2c New approach to r136737: insert the necessary fences for atomic ops in platform-independent code, since a bunch of platforms (ARM, Mips, PPC, Alpha are the relevant targets here) need to do essentially the same thing.
I think this completes the basic CodeGen for atomicrmw and cmpxchg.

llvm-svn: 136813
2011-08-03 21:06:02 +00:00
Evan Cheng
2e96785311 Rename TargetAsmParser to MCTargetAsmParser and TargetAsmLexer to MCTargetAsmLexer; rename createAsmLexer to createMCAsmLexer and createAsmParser to createMCAsmParser.
llvm-svn: 136027
2011-07-26 00:24:13 +00:00
Roman Divacky
a07d8900f5 Set PPCII::MO_DARWIN_STUB only on MacOSX < 10.5.
llvm-svn: 135866
2011-07-24 08:22:56 +00:00
Chris Lattner
e1fe7061ce land David Blaikie's patch to de-constify Type, with a few tweaks.
llvm-svn: 135375
2011-07-18 04:54:35 +00:00
Cameron Zwarich
c23366d357 Add an intrinsic and codegen support for fused multiply-accumulate. The intent
is to use this for architectures that have a native FMA instruction.

llvm-svn: 134742
2011-07-08 21:39:21 +00:00
Roman Divacky
08f7d5cf91 Remove accidentaly left node from previous iteration of the patch.
Noticed by Benjamin Kramer!

llvm-svn: 134376
2011-07-04 15:42:45 +00:00
Roman Divacky
736e37d9b9 Implement ISD::VAARG lowering on PPC32.
llvm-svn: 134005
2011-06-28 15:30:42 +00:00
Roman Divacky
6778c94b24 Fix a few places where 32bit instructions/registerset were used on PPC64.
llvm-svn: 133260
2011-06-17 15:21:10 +00:00
Eli Friedman
3caa6e7fe5 PR10136: fix PPCTargetLowering::LowerCall_SVR4 so that a necessary CopyToReg doesn't appear to be dead.
Roman, since you're writing tests for other PPC-SVR4 vararg-related stuff, would you mind writing a test for this?

llvm-svn: 133018
2011-06-14 22:16:20 +00:00
Eric Christopher
1ae9ec6124 Add a parameter to CCState so that it can access the MachineFunction.
No functional change.

Part of PR6965

llvm-svn: 132763
2011-06-08 23:55:35 +00:00
Roman Divacky
3624922127 Fix wrong usages of CTR/MCTR where CTR8/MCTR8 was meant.
- Check for MTCTR8 in addition to MTCTR when looking up a hazard.

- When lowering an indirect call use CTR8 when targeting 64bit.

- Introduce BCTR8 that uses CTR8 and use it on 64bit when expanding ISD::BRIND.

The last change fixes PR8487. With those changes, we are able to compile a
running "ls" and "sh" on FreeBSD/PowerPC64.

llvm-svn: 132552
2011-06-03 15:47:49 +00:00
Eric Christopher
d68494ffdd Have LowerOperandForConstraint handle multiple character constraints.
Part of rdar://9119939

llvm-svn: 132510
2011-06-02 23:16:42 +00:00
Cameron Zwarich
fa285d651f Make CodeGen/PowerPC/2007-09-11-RegCoalescerAssert.ll pass with the verifier.
llvm-svn: 131627
2011-05-19 03:11:06 +00:00
Eli Friedman
12e590e760 Make the logic for determining function alignment more explicit. No functionality change.
llvm-svn: 131012
2011-05-06 20:34:06 +00:00
Daniel Dunbar
82a4062a4e ADT/Triple: Renambe isOSX... methods to isMacOSX for consistency with the OS
triple component.

llvm-svn: 129838
2011-04-20 00:14:25 +00:00
Daniel Dunbar
685eb363c9 Target/PPC: Eliminate a use of getDarwinVers().
llvm-svn: 129810
2011-04-19 20:57:03 +00:00
Chris Lattner
0304b82f80 Fix a ton of comment typos found by codespell. Patch by
Luis Felipe Strano Moraes!

llvm-svn: 129558
2011-04-15 05:18:47 +00:00
Jakob Stoklund Olesen
c4092e120d Insert code in the right location when lowering PowerPC atomics.
This causes defs to dominate uses, no instructions after terminators, and other
goodness.

llvm-svn: 128836
2011-04-04 17:57:29 +00:00
Jakob Stoklund Olesen
de8d7a7432 Use X0 instead of R0 for the zero register on ppc64.
The 32-bit R0 cannot be used where a 64-bit register is expected.

llvm-svn: 128828
2011-04-04 17:07:06 +00:00
Owen Anderson
bd26993873 Allow targets to specify a the type of the RHS of a shift parameterized on the type of the LHS.
llvm-svn: 126518
2011-02-25 21:41:48 +00:00
Devang Patel
d5c4589795 Revert r124611 - "Keep track of incoming argument's location while emitting LiveIns."
In other words, do not keep track of argument's location.  The debugger (gdb) is not prepared to see line table entries for arguments. For the debugger, "second" line table entry marks beginning of function body.
This requires some coordination with debugger to get this working. 
 - The debugger needs to be aware of prolog_end attribute attached with line table entries.
 - The compiler needs to accurately mark prolog_end in line table entries (at -O0 and at -O1+)

llvm-svn: 126155
2011-02-21 23:21:26 +00:00
Stuart Hastings
47e45a32a8 Swap VT and DebugLoc operands of getExtLoad() for consistency with
other getNode() methods.  Radar 9002173.

llvm-svn: 125665
2011-02-16 16:23:55 +00:00
Devang Patel
97c467ee47 Keep track of incoming argument's location while emitting LiveIns.
llvm-svn: 124611
2011-01-31 21:38:14 +00:00
Jeffrey Yasskin
5f5e1f5ef1 Remove unused variables found by gcc-4.6's -Wunused-but-set-variable.
llvm-svn: 123707
2011-01-18 00:51:23 +00:00
Anton Korobeynikov
cf5967630b Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there.
llvm-svn: 123170
2011-01-10 12:39:04 +00:00
Jeffrey Yasskin
a199652a3e Change all self assignments X=X to (void)X, so that we can turn on a
new gcc warning that complains on self-assignments and
self-initializations.

llvm-svn: 122458
2010-12-23 00:58:24 +00:00
Chris Lattner
65c5243bd6 rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for
something that just glues two nodes together, even if it is
sometimes used for flags.

llvm-svn: 122310
2010-12-21 02:38:05 +00:00
Wesley Peck
d589353ad0 Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.
llvm-svn: 119990
2010-11-23 03:31:01 +00:00
Chris Lattner
e50d695490 convert the operand bits into bitfields since they are all combinable in
different ways.  Add $non_lazy_ptr support, and proper lowering for
global values.

Now all the ppc regression tests pass with the new instruction printer.

llvm-svn: 119106
2010-11-15 03:13:19 +00:00
Chris Lattner
9a0a840839 add targetoperand flags for jump tables, constant pool and block address
nodes to indicate when ha16/lo16 modifiers should be used.  This lets
us pass PowerPC/indirectbr.ll.

The one annoying thing about this patch is that the MCSymbolExpr isn't
expressive enough to represent ha16(label1-label2) which we need on
PowerPC.  I have a terrible hack in the meantime, but this will have
to be revisited at some point.

Last major conversion item left is global variable references.

llvm-svn: 119105
2010-11-15 02:46:57 +00:00
Chris Lattner
3512e07ecf implement support for the MO_DARWIN_STUB TargetOperand flag,
and have isel apply to to call operands as required.  This allows
us to get $stub suffixes on label references on ppc/tiger with the
new instprinter, fixing two tests.  Only 2 to go.

llvm-svn: 119093
2010-11-14 23:42:06 +00:00
Duncan Sands
3bf2a701a5 In the calling convention logic, ValVT is always a legal type,
and as such can be represented by an MVT - the more complicated
EVT is not needed.  Use MVT for ValVT everywhere.

llvm-svn: 118245
2010-11-04 10:49:57 +00:00
Duncan Sands
f6e5e02c9b Inside the calling convention logic LocVT is always a simple
value type, so there is no point in passing it around using
an EVT.  Use the simpler MVT everywhere.  Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.

llvm-svn: 118167
2010-11-03 11:35:31 +00:00
John Thompson
6115a7f1d4 Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support.
llvm-svn: 117667
2010-10-29 17:29:13 +00:00
Duncan Sands
0c166168a0 Remove some variables that are never really used
(gcc-4.6 warns about these).

llvm-svn: 117021
2010-10-21 16:03:28 +00:00
Jakob Stoklund Olesen
a0a5015a35 PowerPC varargs functions store live-in registers on the stack. Make sure we use
virtual registers for those stores since RegAllocFast requires that each live
physreg only be used once.

This fixes PR8357.

llvm-svn: 116222
2010-10-11 20:43:09 +00:00
Chris Lattner
2b428a0ab8 fix the expansion of va_arg instruction on PPC to know the arg
alignment for PPC32/64, avoiding some masking operations.

llvm-gcc expands vaarg inline instead of using the instruction
so it has never hit this.

llvm-svn: 116168
2010-10-10 18:34:00 +00:00