Evan Cheng
|
088f7c51a4
|
LDM_RET restores pc, do not set 's' bit which would restore CPSR from SPSR.
llvm-svn: 58707
|
2008-11-04 17:57:07 +00:00 |
|
Jim Grosbach
|
5262898365
|
Add binary encoding support for multiply instructions. Some blanks left to fill in, but the basics are there.
llvm-svn: 58626
|
2008-11-03 18:38:31 +00:00 |
|
Jim Grosbach
|
d0ff59ec42
|
Update ARM Insn encoding to get endian-ness to match the documentation (31-0 left to right)
llvm-svn: 57524
|
2008-10-14 20:36:24 +00:00 |
|
Evan Cheng
|
f2c04a10e6
|
Fix addrmode1 instruction encodings; fix bx_ret encoding.
llvm-svn: 56277
|
2008-09-17 07:53:38 +00:00 |
|
Evan Cheng
|
d268288d39
|
Specify instruction encoding using range list to avoid endianess issues.
llvm-svn: 56276
|
2008-09-17 07:16:21 +00:00 |
|
Evan Cheng
|
0a3a595612
|
Revert 56176. All those instruction formats are still needed.
llvm-svn: 56180
|
2008-09-13 01:35:33 +00:00 |
|
Evan Cheng
|
18fd8337b3
|
Eliminate unnecessary instruction formats.
llvm-svn: 56176
|
2008-09-12 23:15:39 +00:00 |
|
Evan Cheng
|
66e7651a16
|
Addrmode 1 S bit can be dynamically set. Look for CPSR def.
llvm-svn: 56172
|
2008-09-12 22:45:55 +00:00 |
|
Evan Cheng
|
738426a2a1
|
Control flow instruction encodings.
llvm-svn: 55601
|
2008-09-01 08:25:56 +00:00 |
|
Evan Cheng
|
36170e63a3
|
ldm / stm instruction encodings.
llvm-svn: 55599
|
2008-09-01 07:48:18 +00:00 |
|
Evan Cheng
|
01019d7909
|
AXI2 and AXI3 instruction encodings.
llvm-svn: 55598
|
2008-09-01 07:34:13 +00:00 |
|
Evan Cheng
|
fdae49e627
|
Reorganize instruction formats again; AXI1 encoding.
llvm-svn: 55597
|
2008-09-01 07:19:00 +00:00 |
|
Evan Cheng
|
26305b192f
|
addrmode3 instruction encodings.
llvm-svn: 55596
|
2008-09-01 07:00:14 +00:00 |
|
Evan Cheng
|
eb40cb3e42
|
Reorganize some instruction format definitions. No functionality change.
llvm-svn: 55594
|
2008-09-01 01:51:14 +00:00 |
|
Evan Cheng
|
fa095aec1e
|
Rest of addrmode2 instruction encodings.
llvm-svn: 55593
|
2008-09-01 01:27:33 +00:00 |
|
Evan Cheng
|
4c8338c0d3
|
Addr2 word / byte load encodings.
llvm-svn: 55591
|
2008-08-31 19:02:21 +00:00 |
|
Evan Cheng
|
94f3d276c6
|
Addr1 instructions opcodes are encoded in bits 21-24; encode S bit.
llvm-svn: 55590
|
2008-08-31 18:32:16 +00:00 |
|
Evan Cheng
|
b38decd917
|
addrmode1 (data processing) instruction encoding: bits 5-6 are 0, bits 7-10 encode the opcode.
llvm-svn: 55531
|
2008-08-29 07:40:52 +00:00 |
|
Evan Cheng
|
f90bc9a050
|
More refactoring.
llvm-svn: 55528
|
2008-08-29 06:41:12 +00:00 |
|
Evan Cheng
|
c50df85672
|
Refactor ARM instruction format definitions into a separate file. No functionality changes.
llvm-svn: 55518
|
2008-08-28 23:39:26 +00:00 |
|