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Commit Graph

21527 Commits

Author SHA1 Message Date
Chandler Carruth
d2716ae111 Temporarily revert r158087.
This patch causes problems when both dynamic stack realignment and
dynamic allocas combine in the same function. With this patch, we no
longer build the epilog correctly, and silently restore registers from
the wrong position in the stack.

Thanks to Matt for tracking this down, and getting at least an initial
test case to Chad. I'm going to try to check a variation of that test
case in so we can easily track the fixes required.

llvm-svn: 158654
2012-06-18 07:03:12 +00:00
Hal Finkel
40483bafbf Cleanup trip-count finding for PPC CTR loops (and some bug fixes).
This cleans up the method used to find trip counts in order to form CTR loops on PPC.
This refactoring allows the pass to find loops which have a constant trip count but also
happen to end with a comparison to zero. This also adds explicit FIXMEs to mark two different
classes of loops that are currently ignored.

In addition, we now search through all potential induction operations instead of just the first.
Also, we check the predicate code on the conditional branch and abort the transformation if the
code is not EQ or NE, and we then make sure that the branch to be transformed matches the
condition register defined by the comparison (multiple possible comparisons will be considered).

llvm-svn: 158607
2012-06-16 20:34:07 +00:00
Kay Tiong Khoo
7247ab8114 *no need to pollute Intel syntax with bonus mnemonics; operand size is explicitly specified
llvm-svn: 158603
2012-06-16 17:19:49 +00:00
NAKAMURA Takumi
b10b335713 Mips/AsmParser/CMakeLists.txt: Fix dependency.
llvm-svn: 158602
2012-06-16 15:33:52 +00:00
Kevin Enderby
4964b6a4e2 Fix the encoding of the armv7m (MClass) for MSR registers other than aspr,
iaspr, espr and xpsr which also needed to have 0b10 in their mask encoding bits.

llvm-svn: 158560
2012-06-15 22:14:44 +00:00
Manman Ren
7ffcd63dea ARM: optimization for sub+abs.
This patch will optimize abs(x-y)
FROM
sub, movs, rsbmi
TO
subs, rsbmi

For abs, we will use cmp instead of movs. This is necessary because we already
have an existing peephole pass which optimizes away cmp following sub.

rdar: 11633193
llvm-svn: 158551
2012-06-15 21:32:12 +00:00
Kay Tiong Khoo
a419828b83 *fixed to separate mnemonic from operands with tab
llvm-svn: 158543
2012-06-15 21:04:21 +00:00
Jakob Stoklund Olesen
6fd22231ba Preserve <undef> flags in ARMExpandPseudo.
This probably mostly shows up in bugpoint-generated code.

llvm-svn: 158527
2012-06-15 17:46:54 +00:00
Craig Topper
19cfb998fd Move AVX version of convert instructions that write to GPRs to the Op1 table.
llvm-svn: 158497
2012-06-15 07:02:58 +00:00
Pete Cooper
e1c5e7bf9f Move X86::VCVTTSD2SIrr from the 2 operand to 1 operand MemRegOp table.
Can someone with more knowledge of this please look at other entries
to see if others need moved.

llvm-svn: 158474
2012-06-14 22:12:58 +00:00
Akira Hatanaka
5e9724637e Fix coding style violations. Remove white spaces and tabs.
llvm-svn: 158471
2012-06-14 21:10:56 +00:00
Akira Hatanaka
d1b2b96ed5 1. introduce MipsPat in place of Pat in order to exclude those from
being used by Mips16 or Micro Mips
2. clean up a few lines too long encountered

Patch by Reed Kotler.

llvm-svn: 158470
2012-06-14 21:03:23 +00:00
NAKAMURA Takumi
cf2652ae8c MipsLongBranch.cpp: Tweak llvm::next() to appease msvc.
llvm-svn: 158446
2012-06-14 12:29:48 +00:00
Richard Barton
2a7d06a53e Replace assertion failure for badly formatted CPS instrution with error message.
llvm-svn: 158445
2012-06-14 10:48:04 +00:00
Jush Lu
6dd02e5fe3 Cleanup whitespace.
llvm-svn: 158443
2012-06-14 06:08:19 +00:00
Akira Hatanaka
012069bb89 Fix Mips/CMakeLists.txt.
llvm-svn: 158437
2012-06-14 01:23:55 +00:00
Akira Hatanaka
70ebace503 Add file MipsLongBranch.cpp.
llvm-svn: 158436
2012-06-14 01:22:24 +00:00
Akira Hatanaka
7ea45292fb Remove code in MipsAsmPrinter and MipsMCInstLower.
llvm-svn: 158434
2012-06-14 01:20:12 +00:00
Akira Hatanaka
0d20b51ff7 Add long branch expansion pass for MIPS.
llvm-svn: 158433
2012-06-14 01:19:35 +00:00
Akira Hatanaka
19512459e6 Add AT to the list of registers clobbered by branches so that it is available
as a scratch register when they are expanded to long branches.

llvm-svn: 158432
2012-06-14 01:17:59 +00:00
Akira Hatanaka
fb3c87c739 In MipsRegisterInfo::eliminateFrameIndex, call Mips::loadImmediate
to load an immediate that does not fit into 16-bit. 

llvm-svn: 158431
2012-06-14 01:17:36 +00:00
Akira Hatanaka
415903692b In MipsFrameLowering::emitPrologue and emitEpilogue, call Mips::loadImmediate
to load an immediate that does not fit into 16-bit. Also, take into
consideration the global base register slot on the stack when computing the
stack size. 

llvm-svn: 158430
2012-06-14 01:17:13 +00:00
Akira Hatanaka
8f2f845215 Define function MipsInstrInfo::GetInstSizeInBytes, which will be called to
compute the size of basic blocks in a function. Also, define a function which
emits a series of instructions to load an immediate.

llvm-svn: 158429
2012-06-14 01:16:45 +00:00
Akira Hatanaka
afa4622baf In MipsISelDAGToDAG.cpp, store the global base register to a stack frame object.
Long-branches need access to the global base register to get the destination
address.

llvm-svn: 158428
2012-06-14 01:16:15 +00:00
Akira Hatanaka
2784db9e87 Add methods to MipsFunctionInfo for initializing and accessing the stack frame
object for the global base register.

This is the first of a series of patches which implements long branch expansion
for MIPS.

llvm-svn: 158427
2012-06-14 01:15:36 +00:00
Akira Hatanaka
2f3e3d6ece Bundle jump/branch instructions with the instructions in the delay slot in
delay slot filler pass of MIPS, per suggestion of Jakob Stoklund Olesen.

This change, along with the fix in r158154, enables machine verification
to be run after delay slot filling.

llvm-svn: 158426
2012-06-13 23:25:52 +00:00
Akira Hatanaka
0435101a38 Implement a DAGCombine in MipsISelLowering.cpp which transforms the following
pattern:

(add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))

"tjt" is a TargetJumpTable node. 

llvm-svn: 158419
2012-06-13 20:33:18 +00:00
Akira Hatanaka
fef6359b1c Set a higher value for maxStoresPerMemcpy in MipsISelLowering.cpp.
llvm-svn: 158414
2012-06-13 19:33:32 +00:00
Akira Hatanaka
cf4210f6d7 Simplify CreateLoadLR and CreateStoreLR in MipsISelLowering.cpp.
llvm-svn: 158413
2012-06-13 19:06:08 +00:00
Akira Hatanaka
25f2f1feba Implement fastcc calling convention for MIPS.
llvm-svn: 158410
2012-06-13 18:06:00 +00:00
Richard Osborne
96c0be7351 Fix pattern for MKMSK instruction.
llvm-svn: 158409
2012-06-13 17:59:12 +00:00
Kay Tiong Khoo
b631f7fd59 *typo: Cyles changed to Cycles
llvm-svn: 158404
2012-06-13 15:53:04 +00:00
Craig Topper
b2299168d3 Fix intrinsics for XOP frczss/sd instructions. These instructions only take one source register and zero the upper bits of the destination rather than preserving them.
llvm-svn: 158396
2012-06-13 07:18:53 +00:00
Hal Finkel
021ce0f07b Add another missing 64-bit itinerary definition for the PPC A2 core.
llvm-svn: 158393
2012-06-13 05:55:09 +00:00
Akira Hatanaka
36f518fd08 Clean up trailing blanks in Mips16InstrFormats.td
Patch by Reed Kotler.

llvm-svn: 158382
2012-06-13 02:42:47 +00:00
Akira Hatanaka
c118cf7c71 disable use of directive .set nomicromips
until this directive is pushed in gas to open source fsf

Patch by Reed Kotler.

llvm-svn: 158381
2012-06-13 02:41:14 +00:00
Akira Hatanaka
7e0382b71e 1. fix places where immed is used in place of imm to be consistent with
non mips16
2. fix some comments to change OPcode->EXTEND for extended instructions

Patch by Reed Kotler.

llvm-svn: 158378
2012-06-13 02:37:54 +00:00
Hal Finkel
ad66e9569f Add some missing 64-bit itinerary definitions for the PPC A2 core.
llvm-svn: 158373
2012-06-12 20:32:29 +00:00
Chad Rosier
9734752b2c [arm-fast-isel] Add support for -arm-long-calls.
Patch by Jush Lu <jush.msn@gmail.com>.

llvm-svn: 158368
2012-06-12 19:25:13 +00:00
Hal Finkel
a005be7ae7 Split out the PPC instruction class IntSimple from IntGeneral.
On the POWER7, adds and logical operations can also be handled
in the load/store pipelines. We'll call these IntSimple.

llvm-svn: 158366
2012-06-12 19:01:24 +00:00
Hal Finkel
6a80441b25 Fixes for PPC host detection and features.
POWER4 is a 64-bit CPU (better matched to the 970).
The g3 is really the 750 (no altivec), the g4+ is the 74xx (not the 750).

Patch by Andreas Tobler.

llvm-svn: 158363
2012-06-12 16:39:23 +00:00
Hal Finkel
f29a217a58 Reapply r158337, this time properly protect Darwin/PPC host CPU use with __ppc__.
Original commit message:
Move PPC host-CPU detection logic from PPCSubtarget into sys::getHostCPUName().

Both the new Linux functionality and the old Darwin functions have been moved.
This change also allows this information to be queried directly by clang and
other frontends (clang, for example, will now have real -mcpu=native support).

llvm-svn: 158349
2012-06-12 03:03:13 +00:00
Jakob Stoklund Olesen
dd5f904ac0 Revert r158337 "Move PPC host-CPU detection logic from PPCSubtarget into sys::getHostCPUName()."
This commit broke most of the PowerPC unit tests when running on
Intel/Apple.

llvm-svn: 158345
2012-06-12 00:58:40 +00:00
Hal Finkel
d1e6c8928a Move PPC host-CPU detection logic from PPCSubtarget into sys::getHostCPUName().
Both the new Linux functionality and the old Darwin functions have been moved.
This change also allows this information to be queried directly by clang and
other frontends (clang, for example, will now have real -mcpu=native support).

llvm-svn: 158337
2012-06-11 23:14:31 +00:00
Hal Finkel
6b88059d5e Enable MFOCRF generation on the PPC A2 core.
llvm-svn: 158324
2012-06-11 19:57:04 +00:00
Hal Finkel
fa52a34d78 Rename the PPC target feature gpul to mfocrf.
The PPC target feature gpul (IsGigaProcessor) was only used for one thing:
To enable the generation of the MFOCRF instruction. Furthermore, this
instruction is available on other PPC cores outside of the G5 line. This
feature now corresponds to the HasMFOCRF flag.

No functionality change.

llvm-svn: 158323
2012-06-11 19:57:01 +00:00
Hal Finkel
9d5f414e63 Add A2 to the list of PPC CPUs recognized by Linux host CPU-type detection.
llvm-svn: 158322
2012-06-11 19:56:57 +00:00
Hal Finkel
93a1ca077d Emit the two-operand form of the PPC mfcr instruction as mfocrf.
This is necessary on Linux and supported on Darwin, see PR2604.

llvm-svn: 158315
2012-06-11 15:43:15 +00:00
Hal Finkel
90c0af7137 Add local CPU detection for Linux PPC.
This functionality mirrors that available on PPC/Darwin.

llvm-svn: 158314
2012-06-11 15:43:13 +00:00
Hal Finkel
ab5027a1a2 Add POWER6 and POWER7 CPU types to the PPC backend.
No functional change; these will be used by upcoming scheduler enhancements.

llvm-svn: 158313
2012-06-11 15:43:08 +00:00