RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 19:23:23 +01:00
Code Issues Projects Releases Wiki Activity
81,447 Commits 4 Branches 5 Tags 704 MiB
d36ce9b17b
Commit Graph

81447 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Bill Wendling
f6c626e3a9 Reformatting. No functionality change. 
llvm-svn: 153928
 2012-04-03 03:56:52 +00:00
Bill Wendling
7680143edf As Eric pointed out, even a Debug build should be equal. Leave the flag that can turn off comparisons though. 
llvm-svn: 153927
 2012-04-03 03:27:43 +00:00
Akira Hatanaka
c5bbe0b434 Revert r153924. Delete test/MC/Disassembler/Mips and lib/Target/Mips/Disassembler. 
llvm-svn: 153926
 2012-04-03 03:01:13 +00:00
Akira Hatanaka
cecb440c11 Revert r153924. There were buildbot failures. 
llvm-svn: 153925
 2012-04-03 02:51:09 +00:00
Akira Hatanaka
058b0cfb55 MIPS disassembler support. 
Patch by Vladimir Medic.

llvm-svn: 153924
 2012-04-03 02:20:58 +00:00
Andrew Trick
a1e25f74dd Cleanup set_union usage. The same thing but a bit cleaner now. 
llvm-svn: 153922
 2012-04-03 01:35:52 +00:00
Andrew Trick
a92546a4bb Use std::set_union instead of nasty custom code. 
I just noticed Jakob's examples of the proper application of
std::set... routines.

llvm-svn: 153918
 2012-04-03 00:47:23 +00:00
Eric Christopher
ba40985484 Add a line number for the scope of the function (starting at the first 
brace) so that we get more accurate line number information about the
declaration of a given function and the line where the function
first starts.

Part of rdar://11026482

llvm-svn: 153916
 2012-04-03 00:43:49 +00:00
Pete Cooper
fb86d3b6bc Fixes to r153903. Added missing explanation of behaviour when the VirtRegMap is NULL. Also changed it in this case to just avoid updating the map, but live ranges or intervals will still get updated and created 
llvm-svn: 153914
 2012-04-03 00:28:46 +00:00
Bill Wendling
e3ff2c3ce6 Compare the .o files only for release builds. Add an option to bypass the comparison altogether. 
llvm-svn: 153909
 2012-04-02 23:27:43 +00:00
Pete Cooper
426b167bc5 Moved LiveRangeEdit.h so that it can be called from other parts of the backend, not just libCodeGen 
llvm-svn: 153906
 2012-04-02 22:44:18 +00:00
Rafael Espindola
6363adaa9f Make dominatedBySlowTreeWalk private and assert cases handled by the caller. 
llvm-svn: 153905
 2012-04-02 22:37:54 +00:00
Jakob Stoklund Olesen
97f47c37b6 Allocate virtual registers in ascending order. 
This is just the fallback tie-breaker ordering, the main allocation
order is still descending size.

Patch by Shamil Kurmangaleev!

llvm-svn: 153904
 2012-04-02 22:30:39 +00:00
Pete Cooper
a76a82ef6f Refactored the LiveRangeEdit interface so that MachineFunction, TargetInstrInfo, MachineRegisterInfo, LiveIntervals, and VirtRegMap are all passed into the constructor and stored as members instead of passed in to each method. 
llvm-svn: 153903
 2012-04-02 22:22:53 +00:00
Bill Wendling
1db4186413 Add an option to turn off the expensive GVN load PRE part of GVN. 
llvm-svn: 153902
 2012-04-02 22:16:50 +00:00
Owen Anderson
157487e7c5 Add predicates for checking whether targets have free FNEG and FABS operations, and prevent the DAGCombiner from turning them into bitwise operations if they do. 
llvm-svn: 153901
 2012-04-02 22:10:29 +00:00
Lang Hames
dbc3175c89 During two-address lowering, rescheduling an instruction does not untie 
operands. Make TryInstructionTransform return false to reflect this.
Fixes PR11861.

llvm-svn: 153892
 2012-04-02 19:58:43 +00:00
Rafael Espindola
40e34629cb No need to run llvm-as. 
llvm-svn: 153890
 2012-04-02 19:44:20 +00:00
Akira Hatanaka
f37a1c4323 Initial 64 bit direct object support. 
This patch allows llvm to recognize that a 64 bit object file is being produced
and that the subsequently generated ELF header has the correct information.

The test case checks for both big and little endian flavors.

Patch by Jack Carter.

llvm-svn: 153889
 2012-04-02 19:25:22 +00:00
Hal Finkel
63edfabaaf The binutils for the IBM BG/P are too old to support CFI. 
llvm-svn: 153886
 2012-04-02 19:09:04 +00:00
Hal Finkel
d6e526ae11 Add triple support for the IBM BG/P and BG/Q supercomputers. 
llvm-svn: 153882
 2012-04-02 18:31:33 +00:00
Eric Christopher
6c4e6016b5 Turn on the accelerator tables for Darwin. 
llvm-svn: 153880
 2012-04-02 17:58:52 +00:00
Stepan Dyatkovskiy
0ddc03ebad Fast fix for PR12343: 
http://llvm.org/bugs/show_bug.cgi?id=12343

We have not trivial way for splitting edges that are goes from indirect branch. We can do it with some tricks, but it should be additionally discussed. And it is still dangerous due to difficulty of indirect branches controlling.

Fix forbids this case for unswitching.

llvm-svn: 153879
 2012-04-02 17:16:45 +00:00
Roman Divacky
2460282f66 Implement the SVR4 byval alignment for aggregates. Fixing a FIXME. 
llvm-svn: 153876
 2012-04-02 15:49:30 +00:00
Silviu Baranga
af228a1538 Second part for the 153874 one 
llvm-svn: 153875
 2012-04-02 15:46:46 +00:00
Silviu Baranga
77d372b45e Added fix in TableGen instruction decoder generation. The decoder now breaks for every leaf node. 
llvm-svn: 153874
 2012-04-02 15:20:39 +00:00
Rafael Espindola
1fb406b0fb Add missing 'd'. 
llvm-svn: 153872
 2012-04-02 13:02:57 +00:00
Bill Wendling
ea61af7ff2 Hack the hack. If we have a situation where an ASM object is defined but isn't 
reflected in the LLVM IR (as a declare or something), then treat it like a data
object.

N.B. This isn't 100% correct. The ASM parser should supply more information so
that we know what type of object it is, and what attributes it should have.

llvm-svn: 153870
 2012-04-02 10:01:21 +00:00
Benjamin Kramer
d960cf6265 Emit the asm writer's mnemonic table with SequenceToOffsetTable. 
This way we can get AVX v-prefixed instructions tail merged with the normal insns.

llvm-svn: 153869
 2012-04-02 09:13:46 +00:00
Benjamin Kramer
2f6189e2a5 Move getOpcodeName from the various target InstPrinters into the superclass MCInstPrinter. 
All implementations used the same code.

llvm-svn: 153866
 2012-04-02 08:32:38 +00:00
Craig Topper
52dc5e74e5 Reorder fields in MatchEntry and OperandMatchEntry to reduce padding. A bit tricky due to the target specific sizes for some of the fields so the ordering is only optimal for the targets in the tree. 
llvm-svn: 153865
 2012-04-02 07:48:39 +00:00
Nadav Rotem
a9ec0e024f Optimizing swizzles of complex shuffles may generate additional complex shuffles. 
Do not try to optimize swizzles of shuffles if the source shuffle has more than
a single user, except when the source shuffle is also a swizzle.

llvm-svn: 153864
 2012-04-02 07:11:12 +00:00
Craig Topper
fe02cb5e8b Remove getInstructionName from MCInstPrinter implementations in favor of using the instruction name table from MCInstrInfo. Reduces static data in the InstPrinter implementations. 
llvm-svn: 153863
 2012-04-02 07:01:04 +00:00
Eric Christopher
53e22c484b Fix CXXFLAGS for huge_val.m4. 
Patch by Jeremy Huddleston!

llvm-svn: 153862
 2012-04-02 06:54:01 +00:00
Craig Topper
dbc259a436 Make MCInstrInfo available to the MCInstPrinter. This will be used to remove getInstructionName and the static data it contains since the same tables are already in MCInstrInfo. 
llvm-svn: 153860
 2012-04-02 06:09:36 +00:00
Bill Wendling
8ee5b8754f It could come about that we parse the inline ASM before we get a potential 
definition for it. In that case, we want to wait for the potential definition
before we create a symbol for it.

llvm-svn: 153859
 2012-04-02 03:33:31 +00:00
Craig Topper
949f3bef7a Use SequenceToOffsetTable to generate instruction name table for AsmWriter. 
llvm-svn: 153857
 2012-04-02 00:47:39 +00:00
Chandler Carruth
f2c6dfc460 Start cleaning up the InlineCost class. This switches to sentinel values 
rather than a bitfield, a great suggestion by Chris during code review.

There is still quite a bit of cruft in the interface, but that requires
sorting out some awkward uses of the cost inside the actual inliner.

No functionality changed intended here.

llvm-svn: 153853
 2012-04-01 22:44:09 +00:00
Hal Finkel
e54b93886a Fix some 80-col. violations I introduced with the A2 PPC64 core. 
llvm-svn: 153852
 2012-04-01 21:20:14 +00:00
Hal Finkel
1c045f6845 Enable prefetch generation on PPC64. 
llvm-svn: 153851
 2012-04-01 20:08:17 +00:00
Hal Finkel
415234aaa4 Add LdStSTD* itin. for the PPC64 A2 core. 
llvm-svn: 153850
 2012-04-01 20:08:08 +00:00
Nadav Rotem
2729f54295 This commit contains a few changes that had to go in together. 
1. Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))
   (and also scalar_to_vector).

2. Xor/and/or are indifferent to the swizzle operation (shuffle of one src).
   Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A, B))

3. Optimize swizzles of shuffles:  shuff(shuff(x, y), undef) -> shuff(x, y).

4. Fix an X86ISelLowering optimization which was very bitcast-sensitive.

Code which was previously compiled to this:

movd    (%rsi), %xmm0
movdqa  .LCPI0_0(%rip), %xmm2
pshufb  %xmm2, %xmm0
movd    (%rdi), %xmm1
pshufb  %xmm2, %xmm1
pxor    %xmm0, %xmm1
pshufb  .LCPI0_1(%rip), %xmm1
movd    %xmm1, (%rdi)
ret

Now compiles to this:

movl    (%rsi), %eax
xorl    %eax, (%rdi)
ret

llvm-svn: 153848
 2012-04-01 19:31:22 +00:00
Lang Hames
44174d3b7a Fix typo. 
llvm-svn: 153846
 2012-04-01 19:27:25 +00:00
Hal Finkel
ff17f29a1f Set the default PPC node scheduling preference to ILP (for the embedded cores). 
The 440 and A2 cores have detailed itineraries, and this allows them to be
fully used to maximize throughput.

llvm-svn: 153845
 2012-04-01 19:23:08 +00:00
Hal Finkel
71772b9747 Add ppc440 itin. entries for LdStSTD* 
llvm-svn: 153844
 2012-04-01 19:23:04 +00:00
Hal Finkel
f74994d731 Use full anti-dep. breaking with post-ra sched. on the embedded ppc cores. 
Post-RA scheduling gives a significant performance improvement on
the embedded cores, so turn it on. Using full anti-dep. breaking is
important for FP-intensive blocks, so turn it on (just on the
embedded cores for now; this should also be good on the 970s because
post-ra scheduling is all that we have for now, but that should have
more testing first).

llvm-svn: 153843
 2012-04-01 19:22:57 +00:00
Hal Finkel
fd26145bc6 Add instruction itinerary for the PPC64 A2 core. 
This adds a full itinerary for IBM's PPC64 A2 embedded core. These
cores form the basis for the CPUs in the new IBM BG/Q supercomputer.

llvm-svn: 153842
 2012-04-01 19:22:40 +00:00
Craig Topper
56bc73a030 Use SequenceToOffsetTable to create instruction name table. Saves space particularly on X86 where AVX instructions just add a 'v' to the front of other instructions. 
llvm-svn: 153841
 2012-04-01 18:14:14 +00:00
Benjamin Kramer
84a17ab494 Emit the LLVM<->DWARF register mapping as a sorted table and use binary search to do the lookup. 
This also avoids emitting the information twice, which led to code bloat. On i386-linux-Release+Asserts
with all targets built this change shaves a whopping 1.3 MB off clang. The number is probably exaggerated
by recent inliner changes but the methods were already enormous with the old inline cost computation.

The DWARF reg -> LLVM reg mapping doesn't seem to have holes in it, so it could be a simple lookup table.
I didn't implement that optimization yet to avoid potentially changing functionality.

There is still some duplication both in tablegen and the generated code that should be cleaned up eventually.

llvm-svn: 153837
 2012-04-01 14:23:58 +00:00
Chandler Carruth
8b30ff4d0f Belatedly address some code review from Chris. 
As a side note, I really dislike array_pod_sort... Do we really still
care about any STL implementations that get this so wrong? Does libc++?

llvm-svn: 153834
 2012-04-01 10:41:24 +00:00