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6020 Commits

Author SHA1 Message Date
Rafael Espindola
cd52f85028 fix header 
add comments
untabify

llvm-svn: 30486
 2006-09-19 16:41:40 +00:00
Rafael Espindola
6c7627e002 Implement a MachineFunctionPass to fix the mul instruction 
llvm-svn: 30485
 2006-09-19 15:49:25 +00:00
Chris Lattner
2b076f26b7 item done 
llvm-svn: 30483
 2006-09-19 06:19:03 +00:00
Chris Lattner
92c8924309 Fold the PPCISD shifts when presented with 0 inputs. This occurs for code 
like:
long long test(long long X, int Y) {
  return 1ULL << Y;
}
long long test2(long long X, int Y) {
  return -1LL << Y;
}

which we used to compile to:

_test:
        li r2, 1
        subfic r3, r5, 32
        li r4, 0
        addi r6, r5, -32
        srw r3, r2, r3
        slw r4, r4, r5
        slw r6, r2, r6
        or r3, r4, r3
        slw r4, r2, r5
        or r3, r3, r6
        blr
_test2:
        li r2, -1
        subfic r3, r5, 32
        addi r6, r5, -32
        srw r3, r2, r3
        slw r4, r2, r5
        slw r2, r2, r6
        or r3, r4, r3
        or r3, r3, r2
        blr

Now we produce:

_test:
        li r2, 1
        addi r3, r5, -32
        subfic r4, r5, 32
        slw r3, r2, r3
        srw r4, r2, r4
        or r3, r4, r3
        slw r4, r2, r5
        blr
_test2:
        li r2, -1
        subfic r3, r5, 32
        addi r6, r5, -32
        srw r3, r2, r3
        slw r4, r2, r5
        slw r2, r2, r6
        or r3, r4, r3
        or r3, r3, r2
        blr

llvm-svn: 30479
 2006-09-19 05:22:59 +00:00
Andrew Lenharth
6d43749a47 A pass to remove the worst of the replay trap offenders, and as a bonus, align basic blocks when it is free to do so 
llvm-svn: 30467
 2006-09-18 19:44:29 +00:00
Andrew Lenharth
5d958d3405 Jump tables on Alpha 
llvm-svn: 30463
 2006-09-18 18:01:03 +00:00
Chris Lattner
68009a61c5 add a note. Our 64-bit shifts are ~30% slower than gcc's 
llvm-svn: 30457
 2006-09-18 05:36:54 +00:00
Chris Lattner
a1349de598 This is closer to what we really want. 
llvm-svn: 30451
 2006-09-18 04:54:35 +00:00
Anton Korobeynikov
7c2118575c Added some eye-candy for Subtarget type checking 
Added X86 StdCall & FastCall calling conventions. Codegen will follow.

llvm-svn: 30446
 2006-09-17 20:25:45 +00:00
Anton Korobeynikov
b2b7c2f8b9 Small fixes for supporting dll* linkage types 
llvm-svn: 30441
 2006-09-17 13:06:18 +00:00
Chris Lattner
563785bc55 add a note noticed through source inspection 
llvm-svn: 30418
 2006-09-16 23:57:51 +00:00
Chris Lattner
22b3d6fba9 add a note 
llvm-svn: 30406
 2006-09-16 03:30:19 +00:00
Chris Lattner
bf14089e11 add a nate note 
llvm-svn: 30399
 2006-09-15 20:31:36 +00:00
Evan Cheng
e9bbf85e5e Remove a unnecessary check. 
llvm-svn: 30382
 2006-09-14 23:55:02 +00:00
Chris Lattner
ce85ffa396 add a note 
llvm-svn: 30377
 2006-09-14 20:56:30 +00:00
Anton Korobeynikov
6e19f80688 Adding dllimport, dllexport and external weak linkage types. 
DLL* linkages got full (I hope) codegeneration support in C & both x86
assembler backends.
External weak linkage added for future use, we don't provide any
codegeneration, etc. support for it.

llvm-svn: 30374
 2006-09-14 18:23:27 +00:00
Chris Lattner
0e9985d635 add note about switch lowering 
llvm-svn: 30308
 2006-09-13 23:37:16 +00:00
Evan Cheng
e98acdbf59 Skip over first operand when determining REX prefix for two-address code. 
llvm-svn: 30300
 2006-09-13 19:07:28 +00:00
Chris Lattner
5a00b32eec Turn X < 0 -> TEST X,X js 
llvm-svn: 30294
 2006-09-13 17:04:54 +00:00
Chris Lattner
d2b6dcd4bf The sense of this branch was inverted :( 
llvm-svn: 30293
 2006-09-13 16:56:12 +00:00
Rafael Espindola
1a3020bfcf add shifts to addressing mode 1 
llvm-svn: 30291
 2006-09-13 12:09:43 +00:00
Chris Lattner
89d7fe3917 Fix a regression in the 32-bit port from the 64-bit port landing. 
We now compile CodeGen/X86/lea-2.ll into:

_test:
        movl 4(%esp), %eax
        movl 8(%esp), %ecx
        leal -5(%ecx,%eax,4), %eax
        ret

instead of:

_test:
        movl 4(%esp), %eax
        leal (,%eax,4), %eax
        addl 8(%esp), %eax
        addl $4294967291, %eax
        ret

llvm-svn: 30288
 2006-09-13 04:45:25 +00:00
Chris Lattner
fb0e19072c new note 
llvm-svn: 30286
 2006-09-13 04:19:50 +00:00
Chris Lattner
56e461c7d2 new note 
llvm-svn: 30285
 2006-09-13 03:54:54 +00:00
Chris Lattner
806ef17e5b Compile X > -1 -> text X,X; js dest 
This implements CodeGen/X86/jump_sign.ll.

llvm-svn: 30283
 2006-09-13 03:22:10 +00:00
Evan Cheng
dd52a60189 Reflects MachineConstantPoolEntry changes. 
llvm-svn: 30279
 2006-09-12 21:04:05 +00:00
Chris Lattner
67fe605123 add a note 
llvm-svn: 30271
 2006-09-12 06:36:01 +00:00
Chris Lattner
525974551b Testcase noticed from PR906 
llvm-svn: 30269
 2006-09-11 23:00:56 +00:00
Chris Lattner
e7cd7508ed add compilable testcase 
llvm-svn: 30268
 2006-09-11 22:57:51 +00:00
Rafael Espindola
7722bae67e implement SRL and MUL 
llvm-svn: 30262
 2006-09-11 19:24:19 +00:00
Rafael Espindola
d8b1142d79 add the correct fallback for ARMDAGToDAGISel::SelectAddrMode1 
llvm-svn: 30261
 2006-09-11 19:23:32 +00:00
Rafael Espindola
89ac048c5d partial implementation of the ARM Addressing Mode 1 
llvm-svn: 30252
 2006-09-11 17:25:40 +00:00
Rafael Espindola
a8dd3960f1 call AsmPrinter::doInitialization in ARMAsmPrinter::doInitialization 
llvm-svn: 30246
 2006-09-11 12:49:38 +00:00
Evan Cheng
78f5fae07f Updates. 
llvm-svn: 30245
 2006-09-11 05:35:17 +00:00
Evan Cheng
64720acdb9 Update README file. 
llvm-svn: 30244
 2006-09-11 05:25:15 +00:00
Evan Cheng
cfd7b147cf X86ISD::CMP now produces a chain as well as a flag. Make that the chain 
operand of a conditional branch to allow load folding into CMP / TEST
instructions.

llvm-svn: 30241
 2006-09-11 02:19:56 +00:00
Nate Begeman
1109e4a222 Behold, more work on relocations. Things are looking pretty good now. 
llvm-svn: 30240
 2006-09-10 23:03:44 +00:00
Anton Korobeynikov
4141c7992e Removed unnecessary Mangler creation. 
llvm-svn: 30239
 2006-09-10 21:17:03 +00:00
Chris Lattner
e4ef84f421 Add cbe support for powi 
llvm-svn: 30226
 2006-09-09 06:17:12 +00:00
Nate Begeman
2dfa13e74f First pass at supporting relocations. Relocations are written correctly to 
the file now, however the relocated address is currently wrong.  Fixing
that will require some deep pondering.

llvm-svn: 30207
 2006-09-08 22:42:09 +00:00
Evan Cheng
59e25ca829 Fixed a FuseTwoAddrInst() bug: consider GlobalAddress and JumpTableIndex 
in addition to immediate operands.

llvm-svn: 30205
 2006-09-08 21:08:13 +00:00
Rafael Espindola
20146be5e8 implement shl and sra 
llvm-svn: 30191
 2006-09-08 17:36:23 +00:00
Chris Lattner
6366d97d9e Use __USER_LABEL_PREFIX__ to get the prefix added by the current host. 
llvm-svn: 30190
 2006-09-08 17:03:56 +00:00
Rafael Espindola
9ffcdb8ab7 add the eor (xor) instruction 
llvm-svn: 30189
 2006-09-08 16:59:47 +00:00
Jim Laskey
8cbf601f06 Missing tab 
llvm-svn: 30188
 2006-09-08 13:06:56 +00:00
Rafael Espindola
af1689d5a5 implement unconditional branches 
fix select.ll

llvm-svn: 30186
 2006-09-08 12:47:03 +00:00
Evan Cheng
100e48fe40 Remove TEST64mr. It's same as TEST64rm since and is commutative. 
llvm-svn: 30178
 2006-09-08 06:56:55 +00:00
Evan Cheng
15dd42884e Committing X86-64 support. 
llvm-svn: 30177
 2006-09-08 06:48:29 +00:00
Nate Begeman
bb053826f9 We actually do support object file writing, so don't return true (error) 
llvm-svn: 30173
 2006-09-08 03:42:15 +00:00
Evan Cheng
da0f93c5af - Identify a vector_shuffle that can be turned into an undef, e.g. 
shuffle V1, <undef>, <undef, undef, 4, 5>
- Fix some suspicious logic into LowerVectorShuffle that cause less than
  optimal code by failing to identify MOVL (move to lowest element of a
  vector).

llvm-svn: 30171
 2006-09-08 01:50:06 +00:00
Jim Laskey
160a8aa339 1. Remove condition on delete. 
2. Protect and outline createTargetAsmInfo.

3. Misc. kruft.

llvm-svn: 30169
 2006-09-07 23:39:26 +00:00
Chris Lattner
f4c05c3170 add a new value for the command line optn 
llvm-svn: 30165
 2006-09-07 22:32:28 +00:00
Chris Lattner
6d59598acc Fix a cross-build issue. The asmsyntax shouldn't be affected by the build 
host, it should be affected by the target.  Allow the command line option to
override in either case.

llvm-svn: 30164
 2006-09-07 22:29:41 +00:00
Jim Laskey
9da25f6119 Make target asm info a property of the target machine. 
llvm-svn: 30162
 2006-09-07 22:06:40 +00:00
Jim Laskey
a64fe8ccf2 Break out target asm info into separate files. 
llvm-svn: 30161
 2006-09-07 22:05:02 +00:00
Chris Lattner
9c7673ffca Eliminate X86ISD::TEST, using X86ISD::CMP instead. Match X86ISD::CMP patterns 
using test, which provides nice simplifications like:

-       movl %edi, %ecx
-       andl $2, %ecx
-       cmpl $0, %ecx
+       testl $2, %edi
        je LBB1_11      #cond_next90

There are a couple of dagiselemitter deficiencies that this exposes, they will
be handled later.

llvm-svn: 30156
 2006-09-07 20:33:45 +00:00
Chris Lattner
a96d4ad830 Some notes on better load folding we could do 
llvm-svn: 30155
 2006-09-07 20:32:01 +00:00
Evan Cheng
798aa508a3 Consistency. 
llvm-svn: 30152
 2006-09-07 19:03:48 +00:00
Jim Laskey
d2830c11b8 Make the x86 asm flavor part of the subtarget info. 
llvm-svn: 30146
 2006-09-07 12:23:47 +00:00
Evan Cheng
451baeaf79 Clean up. 
llvm-svn: 30140
 2006-09-07 01:17:57 +00:00
Evan Cheng
5bb0ec5c15 Watch out for variable_ops instructions. 
llvm-svn: 30135
 2006-09-06 20:32:45 +00:00
Evan Cheng
d299a28d86 Variable ops instructions may ignore the last few operands for code emission. 
llvm-svn: 30134
 2006-09-06 20:24:14 +00:00
Jim Laskey
8e922904ce Oops - forgot to update banner. 
llvm-svn: 30131
 2006-09-06 19:21:41 +00:00
Jim Laskey
b3cfa98236 Separate target specifc asm properties from asm printers. 
llvm-svn: 30127
 2006-09-06 18:35:33 +00:00
Jim Laskey
6b86ef852c Separate target specific asm properties from the asm printers. 
llvm-svn: 30126
 2006-09-06 18:34:40 +00:00
Rafael Espindola
d9cebd5e48 add the orr instruction 
llvm-svn: 30125
 2006-09-06 18:03:12 +00:00
Chris Lattner
af7a360ac8 Bugfix to work with the two-addr changes that have been made in the tree recently 
llvm-svn: 30121
 2006-09-05 20:27:32 +00:00
Evan Cheng
24ce2a3b27 Fix a few dejagnu failures. e.g. fast-cc-merge-stack-adj.ll 
llvm-svn: 30113
 2006-09-05 08:32:49 +00:00
Evan Cheng
8ffe1aa35a JIT encoding bug. 
llvm-svn: 30112
 2006-09-05 05:59:25 +00:00
Chris Lattner
fdd2c97fef Update the X86 JIT to make it work with the new two-addr changes. This also 
adds assertions that check to make sure every operand gets emitted.

llvm-svn: 30110
 2006-09-05 02:52:35 +00:00
Chris Lattner
9cd4e3429e Completely eliminate def&use operands. Now a register operand is EITHER a 
def operand or a use operand.

llvm-svn: 30109
 2006-09-05 02:31:13 +00:00
Chris Lattner
59a4d8dfcd Fix a long-standing wart in the code generator: two-address instruction lowering 
actually *removes* one of the operands, instead of just assigning both operands
the same register.  This make reasoning about instructions unnecessarily complex,
because you need to know if you are before or after register allocation to match
up operand #'s with the target description file.

Changing this also gets rid of a bunch of hacky code in various places.

This patch also includes changes to fold loads into cmp/test instructions in
the X86 backend, along with a significant simplification to the X86 spill
folding code.

llvm-svn: 30108
 2006-09-05 02:12:02 +00:00
Andrew Lenharth
a0e57603f0 jmp_bufs are this big on alpha. 
llvm-svn: 30107
 2006-09-05 00:22:25 +00:00
Rafael Espindola
de18749e1f add support for returning 64bit values 
llvm-svn: 30103
 2006-09-04 19:05:01 +00:00
Chris Lattner
53644648df Fix some X86 JIT failures. This should really come from TargetJITInfo. 
llvm-svn: 30102
 2006-09-04 18:48:41 +00:00
Duraid Madina
51396ffd3e add setJumpBufSize() and setJumpBufAlignment() to target-lowering. 
Call these from your backend to enjoy setjmp/longjmp goodness, see
lib/Target/IA64/IA64ISelLowering.cpp for an example

llvm-svn: 30095
 2006-09-04 06:21:35 +00:00
Chris Lattner
33c9ddc91d Completely rearchitect the interface between targets and the pass manager. 
This pass:

1. Splits TargetMachine into TargetMachine (generic targets, can be implemented
any way, like the CBE) and LLVMTargetMachine (subclass of TM that is used by
things using libcodegen and other support).
2. Instead of having each target fully populate the passmgr for file or JIT
   output, move all this to common code, and give targets hooks they can
   implement.
3. Commonalize the target population stuff between file emission and JIT
   emission.
4. All (native code) codegen stuff now happens in a FunctionPassManager, which
   paves the way for "fast -O0" stuff in the CFE later, and now LLC could
   lazily stream .bc files from disk to use less memory.
5. There are now many fewer #includes and the targets don't depend on the
   scalar xforms or libanalysis anymore (but codegen does).
6. Changing common code generator pass ordering stuff no longer requires
   touching all targets.
7. The JIT now has the option of "-fast" codegen or normal optimized codegen,
   which is now orthogonal to the fact that JIT'ing is being done.

llvm-svn: 30081
 2006-09-04 04:14:57 +00:00
Chris Lattner
2ca7348818 Add accessor 
llvm-svn: 30080
 2006-09-04 04:08:58 +00:00
Chris Lattner
98ee856576 remove #include 
llvm-svn: 30078
 2006-09-04 04:06:01 +00:00
Chris Lattner
fb12884be6 Simplify target construction. 
llvm-svn: 30070
 2006-09-03 18:44:02 +00:00
Rafael Espindola
65007fc49c add the SETULT condition code 
llvm-svn: 30067
 2006-09-03 13:19:16 +00:00
Rafael Espindola
5c0443c41e add more condition codes 
llvm-svn: 30056
 2006-09-02 20:24:25 +00:00
Evan Cheng
69ef4ae2a1 Oops. Bad typo. Without the check of N1.hasOneUse() bad things can happen. 
Suppose the TokenFactor can reach the Op:

       [Load chain]
           ^
           |
         [Load]
         ^    ^
         |    |
        /      \-
       /         |
      /          [Op]
     /          ^ ^
     |        ..  |
     |       /    |
   [TokenFactor]  |
       ^          |
       |          |
        \        /
         \      /
         [Store]

If we move the Load below the TokenFactor, we would have created a cycle in
the DAG.

llvm-svn: 30040
 2006-09-01 22:52:28 +00:00
Chris Lattner
fa87f12b85 Use a couple of multiclass patterns to factor some integer ops. 
llvm-svn: 30039
 2006-09-01 22:28:02 +00:00
Chris Lattner
04b7417f40 remove a bunch of comments 
llvm-svn: 30038
 2006-09-01 22:16:22 +00:00
Evan Cheng
366669c860 Minor asm fix. 
llvm-svn: 29965
 2006-08-29 22:14:48 +00:00
Evan Cheng
9fda1129ce Remove dead code. 
llvm-svn: 29962
 2006-08-29 21:42:58 +00:00
Evan Cheng
b747dc2ab0 Don't performance load/op/store transformation if op produces a floating point 
or vector result. X86 does not have load/mod/store variants of those
instructions.

llvm-svn: 29957
 2006-08-29 18:37:37 +00:00
Evan Cheng
4c63a7ed05 - Enable x86 isel preprocessing by default unless -fast is specified. 
- Also disable isel load folding if -fast.

llvm-svn: 29956
 2006-08-29 18:28:33 +00:00
Jim Laskey
d44e9493e6 Handle callee saved registers in dwarf frame info (lead up to exception 
handling.)

llvm-svn: 29954
 2006-08-29 16:24:26 +00:00
Jim Laskey
27420577d7 Tidy up options. 
llvm-svn: 29953
 2006-08-29 15:13:10 +00:00
Evan Cheng
3f6a206f01 Avoid making unneeded load/mod/store transformation which can hurt performance. 
llvm-svn: 29952
 2006-08-29 06:44:17 +00:00
Nate Begeman
a67a1ec1cd Make ppc64 jit kinda work right. About 2/3 of Olden passes with this, 
there are clearly some encoding bugs lurking in there somewhere.

llvm-svn: 29949
 2006-08-29 02:30:59 +00:00
Evan Cheng
dada4aaeee On Mac, print jump table entries after the function to work around a linker issue. 
llvm-svn: 29946
 2006-08-28 22:14:16 +00:00
Evan Cheng
25d25dd384 Add an optional pass to preprocess the DAG before x86 isel to allow selecting more load/mod/store instructions. 
llvm-svn: 29943
 2006-08-28 20:10:17 +00:00
Reid Spencer
2567610703 For PR387: 
Close out this long standing bug by removing the remaining overloaded
virtual functions in LLVM. The -Woverloaded-virtual option is now turned on.

llvm-svn: 29934
 2006-08-28 01:02:49 +00:00
Chris Lattner
33bd5dcfb7 s|llvm/Support/Visibility.h|llvm/Support/Compiler.h| 
llvm-svn: 29911
 2006-08-27 12:54:02 +00:00
Evan Cheng
a6f81f1863 Do not use getTargetNode() and SelectNodeTo() which takes more than 3 
SDOperand arguments. Use the variants which take an array and number instead.

llvm-svn: 29907
 2006-08-27 08:14:06 +00:00
Chris Lattner
3c5fa40194 Fix target matching weights, so that ppc-darwin modules are codegen with the 
ppc target, not the itanium target, when run on an itanium machine.
This should fix the CodeGen/PowerPC regtest failures on itanium.

llvm-svn: 29903
 2006-08-26 21:33:05 +00:00
Evan Cheng
1c3d571e4b SelectNodeTo now returns a SDNode*. 
llvm-svn: 29901
 2006-08-26 08:00:10 +00:00
Evan Cheng
2db7799507 Select() no longer require Result operand by reference. 
llvm-svn: 29898
 2006-08-26 05:34:46 +00:00
Evan Cheng
b246ad7b2f Match tblgen changes. 
llvm-svn: 29895
 2006-08-26 01:07:58 +00:00
Evan Cheng
57893e39fe Match tblgen changes; clean up. 
llvm-svn: 29894
 2006-08-26 01:05:16 +00:00
Chris Lattner
26bde5d791 Give a good error message when we try to jit inline asm. 
llvm-svn: 29891
 2006-08-26 00:47:03 +00:00
Evan Cheng
92239fd096 Add a comment. 
llvm-svn: 29889
 2006-08-25 23:29:06 +00:00
Evan Cheng
ccbb645459 Encode pc-relative conditional branch offset as pc+(num of bytes / 4). The 
asm printer will print it as offset*4. e.g. bne cr0, $+8.

The PPC code emitter was expecting the offset to be number of instructions, not
number of bytes. This fixes a whole bunch of JIT failures.

llvm-svn: 29885
 2006-08-25 21:54:44 +00:00
Jim Laskey
c5bcc6d451 Fix some comments. 
llvm-svn: 29880
 2006-08-25 19:40:59 +00:00
Rafael Espindola
91954ae78f use @ for comments 
store LR in an arbitrary stack slot
add support for writing varargs functions

llvm-svn: 29876
 2006-08-25 17:55:16 +00:00
Chris Lattner
b3ab5fac28 We compile this into: 
_swap_16:
        slwi r2, r3, 24
        rlwimi r2, r3, 8, 8, 15
        srwi r3, r2, 16
        blr

now.

llvm-svn: 29864
 2006-08-24 23:06:02 +00:00
Chris Lattner
b8292ee9e7 Owen implemented this. 
llvm-svn: 29863
 2006-08-24 23:03:33 +00:00
Rafael Espindola
fb63eba81c add the "eq" condition code 
implement a movcond instruction

llvm-svn: 29857
 2006-08-24 17:19:08 +00:00
Rafael Espindola
cf999a6d39 create a generic bcond instruction that has a conditional code argument 
llvm-svn: 29856
 2006-08-24 16:13:15 +00:00
Rafael Espindola
9e2a2dfb2d initial support for branches 
llvm-svn: 29854
 2006-08-24 13:45:55 +00:00
Nate Begeman
1268d6cd46 Initial checkin of the Mach-O emitter. There's plenty of fixmes, but it 
does emit linkable .o files in very simple cases.

llvm-svn: 29850
 2006-08-23 21:08:52 +00:00
Rafael Espindola
af0512fc8d add a README.txt 
llvm-svn: 29814
 2006-08-22 12:22:46 +00:00
Rafael Espindola
474f6c5bf1 initial support for select 
llvm-svn: 29802
 2006-08-21 22:00:32 +00:00
Rafael Espindola
13eb38e699 add the and instruction 
llvm-svn: 29793
 2006-08-21 13:58:59 +00:00
Rafael Espindola
c255c4c434 call computeRegisterProperties 
llvm-svn: 29780
 2006-08-20 01:49:49 +00:00
Chris Lattner
db290f7479 Constify some methods. Patch provided by Anton Vayvod, thanks! 
llvm-svn: 29756
 2006-08-17 22:00:08 +00:00
Chris Lattner
f92824aa27 Revert this patch, the front-end has been fixed to make it unneccesary. 
llvm-svn: 29752
 2006-08-17 18:43:24 +00:00
Chris Lattner
989f26b766 'g' is handled by the front-end. 
llvm-svn: 29751
 2006-08-17 18:12:28 +00:00
Andrew Lenharth
e720e5c444 Fix handling of 'g'. Closes 883 
llvm-svn: 29750
 2006-08-17 17:50:12 +00:00
Rafael Espindola
ff879761c1 add a "load effective address" 
llvm-svn: 29748
 2006-08-17 17:09:40 +00:00
Andrew Lenharth
bea8a84eb1 Add the 'c' constraint as needed by the linux kernel 
llvm-svn: 29747
 2006-08-17 16:07:50 +00:00
Andrew Lenharth
7fdc3bbbcf Add support for S and D constraints, as needed to compile the linux kernel. 
llvm-svn: 29746
 2006-08-17 15:35:43 +00:00
Evan Cheng
33c5017ffb Doh. Incorrectly inverted condition. Also add a isOnlyUse check to match tablegen. 
llvm-svn: 29741
 2006-08-16 23:59:00 +00:00
Rafael Espindola
b98e92cb78 Declare the callee saved regs 
Remove the hard coded store and load of the link register
Implement ARMFrameInfo

llvm-svn: 29727
 2006-08-16 14:43:33 +00:00
Evan Cheng
7fb75bbc8d SelectNodeTo() may return a SDOperand that is different from the input. 
llvm-svn: 29726
 2006-08-16 07:30:09 +00:00
Evan Cheng
af3e059bc4 RET_FLAG has an optional input flag, but it does not produce a flag result. 
llvm-svn: 29725
 2006-08-16 07:28:58 +00:00
Chris Lattner
7476a6c710 add a note 
llvm-svn: 29722
 2006-08-16 02:47:44 +00:00
Chris Lattner
2c12a719c0 Fix PowerPC/2006-08-15-SelectionCrash.ll and simplify selection code. 
llvm-svn: 29715
 2006-08-15 23:48:22 +00:00
Rafael Espindola
48bed9023d select code like 
ldr rx, [ry, #offset]

llvm-svn: 29664
 2006-08-14 19:01:24 +00:00
Nate Begeman
0e92042770 Emit .set directives for jump table entries when possible, which reduces 
the number of relocations in object files, shrinkifying them.

llvm-svn: 29650
 2006-08-12 21:29:52 +00:00
Chris Lattner
c482a5d057 Fix a bug in a recent refactoring that broke a bunch of stuff. 
llvm-svn: 29649
 2006-08-12 07:20:05 +00:00
Chris Lattner
92774dab5c eliminate extraneous blank line 
llvm-svn: 29627
 2006-08-11 21:08:16 +00:00
Chris Lattner
8ca6e82bce Eliminate use of getNode that takes a vector. 
llvm-svn: 29614
 2006-08-11 17:38:39 +00:00
Chris Lattner
be2765058e elimiante use of getNode that takes vector of operands. 
llvm-svn: 29612
 2006-08-11 17:22:35 +00:00
Chris Lattner
c3ce410ac3 eliminate use of getNode that takes vector of operands. 
llvm-svn: 29611
 2006-08-11 17:21:12 +00:00
Chris Lattner
4764bb3834 eliminate use of getNode that takes vector<SDOperand>. Wrap a really long line. 
llvm-svn: 29610
 2006-08-11 17:19:54 +00:00
Chris Lattner
2f9c4426fc Convert vectors to fixed sized arrays and smallvectors. Eliminate use of getNode that takes a vector. 
llvm-svn: 29609
 2006-08-11 17:18:05 +00:00
Chris Lattner
7e905fba17 Fix miscompilation of float vector returns. Compile code to this: 
_func:
        vsldoi v2, v3, v2, 12
        vsldoi v2, v2, v2, 4
        blr

instead of:

_func:
        vsldoi v2, v3, v2, 12
        vsldoi v2, v2, v2, 4
***     vor f1, v2, v2
        blr

llvm-svn: 29607
 2006-08-11 16:47:32 +00:00
Evan Cheng
6053206580 Match tablegen changes. 
llvm-svn: 29604
 2006-08-11 09:08:15 +00:00
Evan Cheng
34a49551f5 CALLSEQ_* produces chain even if that's not needed. 
llvm-svn: 29603
 2006-08-11 09:03:33 +00:00
Evan Cheng
131c832304 Convert more calls of getNode() that takes a vector to pass in the start of an array. 
llvm-svn: 29601
 2006-08-11 07:35:45 +00:00
Rafael Espindola
2ddcf46717 correctly set LocalAreaOffset of TargetFrameInfo 
llvm-svn: 29589
 2006-08-09 17:37:45 +00:00
Rafael Espindola
f0b265b48b fix the spill code 
llvm-svn: 29583
 2006-08-09 16:41:12 +00:00
Rafael Espindola
9e8af5c486 fix the loading of the link register in emitepilogue 
llvm-svn: 29580
 2006-08-09 13:15:47 +00:00
Rafael Espindola
ae2d1c53c7 change the addressing mode of the str instruction to reg+imm 
llvm-svn: 29571
 2006-08-08 20:35:03 +00:00
Rafael Espindola
7bfbb91f75 initial support for variable number of arguments 
llvm-svn: 29567
 2006-08-08 13:02:29 +00:00
Chris Lattner
7b1362fa52 Start eliminating temporary vectors used to create DAG nodes. Instead, pass 
in the start of an array and a count of operands where applicable.  In many
cases, the number of operands is known, so this static array can be allocated
on the stack, avoiding the heap.  In many other cases, a SmallVector can be
used, which has the same benefit in the common cases.

I updated a lot of code calling getNode that takes a vector, but ran out of
time.  The rest of the code should be updated, and these methods should be
removed.

We should also do the same thing to eliminate the methods that take a
vector of MVT::ValueTypes.

It would be extra nice to convert the dagiselemitter to avoid creating vectors
for operands when calling getTargetNode.

llvm-svn: 29566
 2006-08-08 02:23:42 +00:00
Evan Cheng
01cd84d113 Eliminate reachability matrix. It has to be calculated before any instruction 
selection is done. That's rather expensive especially in situations where it
isn't really needed.
Move back to a searching the predecessors, but make use of topological order
to trim the search space.

llvm-svn: 29559
 2006-08-08 00:31:00 +00:00
Evan Cheng
d18be1d9c1 Match tablegen isel changes. 
llvm-svn: 29549
 2006-08-07 22:28:20 +00:00
Evan Cheng
5d8f227a4a Make XMM, FP register dwarf register numbers consistent with gcc. 
llvm-svn: 29543
 2006-08-07 21:02:39 +00:00
Rafael Espindola
bd29d36be4 use a 'register pressure reducing' scheduler 
make sure only one move is used in a hello world

llvm-svn: 29520
 2006-08-04 12:48:42 +00:00
Rafael Espindola
97918b1d11 Bug fix: always generate a RET_FLAG in LowerRET 
fixes ret_null.ll and call.ll

llvm-svn: 29519
 2006-08-03 22:50:11 +00:00
Chris Lattner
0b8dd1f32f remove some more dead sparcv9 support stuff 
llvm-svn: 29506
 2006-08-03 18:55:44 +00:00
Chris Lattner
92e5f0a118 remove a dead proto 
llvm-svn: 29505
 2006-08-03 18:51:04 +00:00
Jim Laskey
a2080b26b9 Get darwin intel debugging up and running. 
llvm-svn: 29504
 2006-08-03 17:27:09 +00:00
Rafael Espindola
fa94338687 add and use ARMISD::RET_FLAG 
llvm-svn: 29499
 2006-08-03 17:02:20 +00:00
Evan Cheng
445674348f Reflect change to AssignTopologicalOrder(). 
llvm-svn: 29480
 2006-08-02 22:01:32 +00:00
Evan Cheng
6fd2b20b8a Use of vector<bool> causes some horrendous compile time regression (2x)! 
Looks like libstdc++ implementation does not scale very well. Switch back
to using directly managed arrays.

llvm-svn: 29469
 2006-08-02 09:18:33 +00:00
Nate Begeman
7d4b0d0b9b Update the readme to remove duplicate information and clarify the loop 
problem.

llvm-svn: 29468
 2006-08-02 05:31:20 +00:00
Nate Begeman
d22dd0f92b Disable LSR at -fast 
llvm-svn: 29467
 2006-08-02 05:29:40 +00:00
Rafael Espindola
719336441f start comments with # 
move the constant pool to .text
correctly print loads of labels
mark R0, R1, R2 and R3 as caller save

llvm-svn: 29451
 2006-08-01 18:53:10 +00:00
Rafael Espindola
f11277971f implement LowerConstantPool and LowerGlobalAddress 
llvm-svn: 29433
 2006-08-01 12:58:43 +00:00
Evan Cheng
29d6f9d252 Factor topological order code to SelectionDAG. Clean up. 
llvm-svn: 29430
 2006-08-01 08:17:22 +00:00
Chris Lattner
26ff12f7f5 Fix PR850 and CodeGen/X86/2006-07-31-SingleRegClass.ll. 
The CFE refers to all single-register constraints (like "A") by their 16-bit
name, even though the 8 or 32-bit version of the register may be needed.
The X86 backend should realize what is going on and redecode the name back
to its proper form.

llvm-svn: 29420
 2006-07-31 23:26:50 +00:00
Rafael Espindola
0ea0399411 handle GlobalValue::InternalLinkage in doFinalization 
llvm-svn: 29417
 2006-07-31 20:38:13 +00:00
Evan Cheng
92eb9a1639 Remove a duplicate pattern. 
llvm-svn: 29414
 2006-07-31 18:43:10 +00:00
Evan Cheng
7e30f4efe7 Remove a duplicate pattern/ 
llvm-svn: 29413
 2006-07-31 18:42:49 +00:00
Chris Lattner
8cb78a0d45 Make functions with an "asm" name propagate that asm name into the cbe.c file. 
This fixes link errors on programs with these on targets with prefixes.

llvm-svn: 29390
 2006-07-28 20:58:47 +00:00
Chris Lattner
51e1b75fba Fix some ppc64 issues with vector code. 
llvm-svn: 29384
 2006-07-28 16:45:47 +00:00
Evan Cheng
e4c19806cd Can't spell. 
llvm-svn: 29383
 2006-07-28 06:33:41 +00:00
Evan Cheng
8ea5ac0abd Some clean up. 
llvm-svn: 29382
 2006-07-28 06:05:06 +00:00
Evan Cheng
5f0e94c299 Rename IsFoldableBy to CanBeFoldedleBy 
llvm-svn: 29376
 2006-07-28 01:03:48 +00:00
Evan Cheng
c43a75b7d4 Node selected into address mode cannot be folded. 
llvm-svn: 29374
 2006-07-28 00:49:31 +00:00
Evan Cheng
3b5f1c6248 Remove InFlightSet hack. No longer needed. 
llvm-svn: 29373
 2006-07-28 00:47:19 +00:00
Evan Cheng
8920047e85 Another duh. Determine topological order before any target node is added. 
llvm-svn: 29371
 2006-07-28 00:10:59 +00:00
Evan Cheng
9d43eb616a Brain cramp.. 
llvm-svn: 29370
 2006-07-27 23:35:40 +00:00
Evan Cheng
24b41a766b Allocating too large an array for ReachibilityMatrix. 
llvm-svn: 29367
 2006-07-27 22:35:40 +00:00
Evan Cheng
17ccdcc415 Calculate the portion of reachbility matrix on demand. 
llvm-svn: 29366
 2006-07-27 22:10:00 +00:00
Evan Cheng
6a126e3adb isNonImmUse is replaced by IsFoldableBy 
llvm-svn: 29365
 2006-07-27 21:19:10 +00:00
Evan Cheng
4ceeac4159 Resolve BB references with relocation. 
llvm-svn: 29351
 2006-07-27 18:21:10 +00:00
Evan Cheng
f363ae6ebd synchronizeICache removeed from TargetJITInfo. 
llvm-svn: 29348
 2006-07-27 17:33:48 +00:00
Evan Cheng
dbcca8f422 Use reachbility information to determine whether a node can be folded into another during isel. 
llvm-svn: 29346
 2006-07-27 16:44:36 +00:00
Rafael Espindola
c0ede90402 emit global constants 
llvm-svn: 29344
 2006-07-27 11:38:51 +00:00
Evan Cheng
e869883c2d Remove NodeDepth 
llvm-svn: 29338
 2006-07-27 06:40:15 +00:00
Chris Lattner
92a0b69813 Add some advice 
llvm-svn: 29324
 2006-07-27 04:24:14 +00:00
Jim Laskey
046abcdbec Use the predicate. 
llvm-svn: 29322
 2006-07-27 02:05:13 +00:00
Nate Begeman
3d5f5b4e8b Support jump tables when in PIC relocation model 
llvm-svn: 29318
 2006-07-27 01:13:04 +00:00
Jim Laskey
f35dd1a670 Prevent creation of MachineDebugInfo for intel unless it is darwin. RC842. 
llvm-svn: 29317
 2006-07-27 01:12:23 +00:00
Evan Cheng
27c53dc36e New entry. 
llvm-svn: 29310
 2006-07-26 21:49:52 +00:00
Chris Lattner
b4165c39d7 Rename RelocModel::PIC to PIC_, to avoid conflicts with -DPIC. 
llvm-svn: 29307
 2006-07-26 21:12:04 +00:00
Evan Cheng
beeb4e5c8c - Refactor the code that resolve basic block references to a TargetJITInfo 
method.
- Added synchronizeICache() to TargetJITInfo. It is called after each block
  of code is emitted to flush the icache. This ensures correct execution
  on targets that have separate dcache and icache.
- Added PPC / Mac OS X specific code to do icache flushing.

llvm-svn: 29276
 2006-07-25 20:40:54 +00:00
Evan Cheng
692215be9c Can't commute shufps. The high / low parts elements come from different vectors. 
llvm-svn: 29275
 2006-07-25 20:25:40 +00:00
Rafael Espindola
2919d4ce24 implement function calling of functions with up to 4 arguments 
llvm-svn: 29274
 2006-07-25 20:17:20 +00:00
Evan Cheng
56e0c65937 Done. 
llvm-svn: 29262
 2006-07-21 23:07:23 +00:00
Rafael Espindola
9ea0bc742c implemented sub 
correctly update the stack pointer in the prologue and epilogue

llvm-svn: 29244
 2006-07-21 12:26:16 +00:00
Evan Cheng
ed1c019899 This opt is now handled in DAG combine. 
llvm-svn: 29243
 2006-07-21 08:26:46 +00:00
Evan Cheng
56434b7578 A splat of a vector constant of all zero or all one is the vector constant. 
llvm-svn: 29234
 2006-07-20 23:09:47 +00:00
Evan Cheng
a634c2b838 Missing a space. 
llvm-svn: 29233
 2006-07-20 22:52:28 +00:00
Evan Cheng
100096b2bb Clean up. 
llvm-svn: 29228
 2006-07-20 21:37:39 +00:00
Evan Cheng
6e440c39da New entry. 
llvm-svn: 29215
 2006-07-19 21:29:30 +00:00
Jim Laskey
5d139b794a Do once flag never set to true. 
llvm-svn: 29214
 2006-07-19 19:33:08 +00:00
Jim Laskey
88d7595eb3 Tidy up a few things. 
llvm-svn: 29213
 2006-07-19 19:32:06 +00:00
Jim Laskey
d31b3778d8 Reduce size of routine. Shrinks .o by 37%. 
llvm-svn: 29210
 2006-07-19 17:53:32 +00:00
Chris Lattner
0f4e4b1bcb bswapped load/store instructions are only availble in indexed addressing form. 
As such, use xoaddr (indexed only), not xaddr for address selection.

This fixes CodeGen/PowerPC/2006-07-19-stwbrx-crash.ll, a crash compiling lencod.

llvm-svn: 29208
 2006-07-19 17:15:36 +00:00
Jim Laskey
227b585c6e Bug#834 ICE (crash in code generator?) when building PCH . 
Missing Darwin check in Intel ATT ASM printer.

llvm-svn: 29204
 2006-07-19 11:54:50 +00:00
Evan Cheng
793f3d97ff Misc. new entry. 
llvm-svn: 29202
 2006-07-19 06:06:24 +00:00
Evan Cheng
a2eaed93a0 INC / DEC instructions have shorter code size than ADD32ri8, etc. 
llvm-svn: 29194
 2006-07-19 00:27:29 +00:00
Evan Cheng
abd650f034 Add code size to target instruction use it as the 3rd isel sorting tie-breaker. 
llvm-svn: 29193
 2006-07-19 00:24:41 +00:00
Rafael Espindola
ad256854c0 initial prologue and epilogue implementation. Need to define add and sub before finishing it :-) 
llvm-svn: 29175
 2006-07-18 17:00:30 +00:00
Chris Lattner
5985b77fae Make the implicit def instructions look like other instrs. 
llvm-svn: 29174
 2006-07-18 16:33:26 +00:00
Rafael Espindola
40073f5767 skeleton of a lowerCall implementation for ARM 
llvm-svn: 29159
 2006-07-16 01:02:57 +00:00
Chris Lattner
f022962081 Remove what little AIX support we have. It has never been tested and isn't 
complete.

llvm-svn: 29156
 2006-07-15 01:24:23 +00:00
Chris Lattner
0f2560a313 Add an out-of-line virtual method for X86DwarfWriter to give it a home. 
llvm-svn: 29153
 2006-07-14 23:05:05 +00:00
Chris Lattner
ff8ee5486f Add missing PPC64 extload/truncstores 
llvm-svn: 29140
 2006-07-14 04:42:02 +00:00
Chris Lattner
9aafd2b441 Add a note 
llvm-svn: 29139
 2006-07-14 04:07:29 +00:00
Chris Lattner
5c489bce2c Another fix in the rotate encodings, needed when the first two operands are not 
the same.

llvm-svn: 29136
 2006-07-13 21:52:41 +00:00
Chris Lattner
753e4f5984 Print negative immediates as negative values instead of large constants 
when using the immshifted addressing mode.

llvm-svn: 29130
 2006-07-12 23:24:02 +00:00
Chris Lattner
726ca018c0 Fix encoding of rotates, such as rldicl 
llvm-svn: 29128
 2006-07-12 22:08:13 +00:00
Chris Lattner
024af03a3c Implement PPC64 relocations types 
llvm-svn: 29125
 2006-07-12 21:23:20 +00:00
Chris Lattner
c9be3277e7 An overaggressive #ifdef allows a function to fall off the bottom of the 
function instead of returning a value.  This sometimes allowed the ppc32 jit
to be used in 64-bit mode.

llvm-svn: 29123
 2006-07-12 20:42:10 +00:00
Chris Lattner
d0202bbed3 Add information preventing several register class constraints from working. 
This implements PR828 and CodeGen/X86/2006-07-12-InlineAsmQConstraint.ll

llvm-svn: 29118
 2006-07-12 16:59:49 +00:00
Chris Lattner
fd9cbcab4a The PPC64 JIT needs register numbers to encode instructions. 
llvm-svn: 29114
 2006-07-11 20:53:55 +00:00
Evan Cheng
db529debec Emit inc / dec of registers as one byte instruction. 
llvm-svn: 29110
 2006-07-11 19:49:49 +00:00
Jim Laskey
d19ba2cf6c It was pointed out that DEBUG() is only available with -debug. 
llvm-svn: 29106
 2006-07-11 18:25:13 +00:00
Jim Laskey
4c0d841280 Ensure that dump calls that are associated with asserts are removed from 
non-debug build.

llvm-svn: 29105
 2006-07-11 17:58:07 +00:00
Rafael Espindola
fdfaee67f5 add the memri memory operand 
this makes it possible for ldr instructions with non-zero immediate

llvm-svn: 29103
 2006-07-11 11:36:48 +00:00
Chris Lattner
b75fe307e1 Implement the inline asm 'A' constraint. This implements PR825 and 
CodeGen/X86/2006-07-10-InlineAsmAConstraint.ll

llvm-svn: 29101
 2006-07-11 02:54:03 +00:00
Chris Lattner
2db97248f8 In 64-bit mode, 64-bit GPRs are callee saved, not 32-bit ones. 
llvm-svn: 29096
 2006-07-11 00:48:23 +00:00
Evan Cheng
7c11ad2f8d New entry. 
llvm-svn: 29091
 2006-07-10 21:42:16 +00:00
Evan Cheng
b5e6a4a74d Fixed stack objects do not specify alignments, but their offsets are known. 
Use that information when doing the transformation to merge multiple loads
into a 128-bit load.

llvm-svn: 29090
 2006-07-10 21:37:44 +00:00
Chris Lattner
abaaddc214 Implement Regression/CodeGen/PowerPC/bswap-load-store.ll by folding bswaps 
into i16/i32 load/stores.

llvm-svn: 29089
 2006-07-10 20:56:58 +00:00
Chris Lattner
18c77b92a9 Mark internal function static 
llvm-svn: 29085
 2006-07-10 19:53:12 +00:00
Rafael Espindola
071c83dff0 create the raddr addressing mode that matches any register and the frame index 
use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot

llvm-svn: 29079
 2006-07-10 01:41:35 +00:00
Evan Cheng
d460c903b1 Fix a typo that causes 2006-07-07-ComputeMaskedBits.ll to fail. 
llvm-svn: 29072
 2006-07-07 21:37:21 +00:00
Evan Cheng
1d48a494a2 X86 target specific DAG combine: turn build_vector (load x), (load x+4), 
(load x+8), (load x+12), <0, 1, 2, 3> to a single 128-bit load (aligned and
unaligned).

e.g.

__m128 test(float a, float b, float c, float d) {
  return _mm_set_ps(d, c, b, a);
}

_test:
        movups 4(%esp), %xmm0
        ret

llvm-svn: 29042
 2006-07-07 08:33:52 +00:00
Chris Lattner
da960e218f Undisable ppc64 jit 
llvm-svn: 29011
 2006-07-06 17:10:42 +00:00
Evan Cheng
a6c9288186 Added option -code-model to set code model (only used in 64-bit) mode. Valid 
values include small, kernel, medium, large, and default.

llvm-svn: 29009
 2006-07-06 01:53:36 +00:00
Evan Cheng
801ea78096 Reorg. No functionality change. 
llvm-svn: 28999
 2006-07-05 22:17:51 +00:00
Evan Cheng
d75aed0d60 Fix JIT on non MacOS X i386 systems. 
llvm-svn: 28992
 2006-07-05 07:09:13 +00:00
Andrew Lenharth
9ea557b06b These are already implemented 
llvm-svn: 28990
 2006-07-03 18:00:29 +00:00
Andrew Lenharth
98f5e9c45a 0 offsets for memory operands 
llvm-svn: 28989
 2006-07-03 17:57:34 +00:00
Evan Cheng
0df13a4f2a Should just use xorps to clear XMM registers for all data types. pxor is also one byte longer. 
llvm-svn: 28984
 2006-06-29 18:04:54 +00:00
Evan Cheng
5a7af4f99f Let X86CompilationCallback pass previous frame and return address to X86CompilationCallback2. Remove alloca hack. 
llvm-svn: 28982
 2006-06-29 01:48:36 +00:00
Evan Cheng
1d5fa40da3 Add shift and rotate by 1 instructions / patterns. 
llvm-svn: 28980
 2006-06-29 00:36:51 +00:00
Evan Cheng
803891eaa8 Always use xorps to clear XMM registers. 
llvm-svn: 28979
 2006-06-29 00:34:23 +00:00
Evan Cheng
1b53896495 Move .literal4 and .literal8 support into AsmPrinter.cpp 
llvm-svn: 28978
 2006-06-29 00:33:06 +00:00
Chris Lattner
adc7078c98 Hide x86 symbols 
llvm-svn: 28976
 2006-06-28 23:27:49 +00:00