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d43e99897c
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376 Commits

Author SHA1 Message Date
Akira Hatanaka
d43e99897c Expand DYNAMIC_STACKALLOC nodes rather than doing custom-lowering. 
The frame object which points to the dynamically allocated area will not be
needed after changes are made to cease reserving call frames.

llvm-svn: 161076
 2012-07-31 20:54:48 +00:00
Akira Hatanaka
85ddbf2e38 When store nodes or memcpy nodes are created to copy the function call 
arguments to the stack in MipsISelLowering::LowerCall, use stack pointer and
integer offset operands rather than frame object operands.

llvm-svn: 161068
 2012-07-31 18:46:41 +00:00
Akira Hatanaka
aab47c049b Fix type of LUXC1 and SUXC1. These instructions were incorrectly defined as 
single-precision load and store.

Also avoid selecting LUXC1 and SUXC1 instructions during isel. It is incorrect
to map unaligned floating point load/store nodes to these instructions.

llvm-svn: 161063
 2012-07-31 18:16:49 +00:00
Akira Hatanaka
9a1f4df56a Pass the correct call frame size to callseq_start node. This is needed to 
replace uses of function getMaxCallFrameSize defined in MipsFunctionInfo with
the one MachineFrameInfo has.

llvm-svn: 160841
 2012-07-26 23:27:01 +00:00
Akira Hatanaka
92df819965 Fix call setup for PIC. 
Patch by Reed Kotler.

llvm-svn: 160774
 2012-07-26 02:24:43 +00:00
Akira Hatanaka
b1ba835c42 Add basic ability to setup call frame, and make procedure calls. 
Hello world will compile and execute with this patch.

Patch by Reed Kotler.

llvm-svn: 160651
 2012-07-23 23:45:54 +00:00
Akira Hatanaka
734a4a8569 Revert accidental commit. 
llvm-svn: 160598
 2012-07-21 02:20:33 +00:00
Akira Hatanaka
e87a027c19 Add VK_Mips_HIGHER and VK_Mips_HIGHEST to MCSymbolRefExpr::VariantKind. 
Test case will be added later when long branch patch is checked in.

llvm-svn: 160597
 2012-07-21 02:15:19 +00:00
Akira Hatanaka
2e26e543b9 Implement MipsTargetLowering::LowerSELECT_CC to custom lower SELECT_CC. 
llvm-svn: 160064
 2012-07-11 19:32:27 +00:00
Akira Hatanaka
aad21ac7f2 Lower RETURNADDR node in Mips backend. 
Patch by Sasa Stankovic.

llvm-svn: 160031
 2012-07-11 00:53:32 +00:00
Akira Hatanaka
96b3eb563a Make register Mips::RA allocatable if not in mips16 mode. 
llvm-svn: 159971
 2012-07-10 00:19:06 +00:00
Jack Carter
0e58c3f697 mips32 long long register inline asm constraint support. 
inlineasm-cnstrnt-bad-r-1.ll is NOT supposed to fail, so it was removed.    This resulted in the removal of a negative test (inlineasm-cnstrnt-bad-r-1.ll)
    

llvm-svn: 159625
 2012-07-02 23:35:23 +00:00
Eric Christopher
07e1aa6bfe Revert " mips32 long long register inline asm constraint support." as 
it appears to be breaking the bots.

This reverts commit 1b055ce320fa13f6f1ac81670d11b45e01f79876.

llvm-svn: 159619
 2012-07-02 23:22:25 +00:00
Jack Carter
64aeffc069 mips32 long long register inline asm constraint support. 
inlineasm-cnstrnt-bad-r-1.ll is NOT supposed to fail, so it was removed.    This resulted in the removal of a negative test (inlineasm-cnstrnt-bad-r-1.ll)
    

llvm-svn: 159610
 2012-07-02 22:39:45 +00:00
Akira Hatanaka
5e9724637e Fix coding style violations. Remove white spaces and tabs. 
llvm-svn: 158471
 2012-06-14 21:10:56 +00:00
Akira Hatanaka
0435101a38 Implement a DAGCombine in MipsISelLowering.cpp which transforms the following 
pattern:

(add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))

"tjt" is a TargetJumpTable node. 

llvm-svn: 158419
 2012-06-13 20:33:18 +00:00
Akira Hatanaka
fef6359b1c Set a higher value for maxStoresPerMemcpy in MipsISelLowering.cpp. 
llvm-svn: 158414
 2012-06-13 19:33:32 +00:00
Akira Hatanaka
cf4210f6d7 Simplify CreateLoadLR and CreateStoreLR in MipsISelLowering.cpp. 
llvm-svn: 158413
 2012-06-13 19:06:08 +00:00
Akira Hatanaka
25f2f1feba Implement fastcc calling convention for MIPS. 
llvm-svn: 158410
 2012-06-13 18:06:00 +00:00
Akira Hatanaka
f860bcf5fc Fix a bug in MipsTargetLowering::LowerLOAD. A shift-right-logical node is 
inserted after the shift-left-logical node.

llvm-svn: 157937
 2012-06-04 17:46:29 +00:00
Hans Wennborg
ff55c96bc2 MIPS TLS: use the model selected by TargetMachine::getTLSModel(). 
This was mostly done already in r156162, but I missed one place.

llvm-svn: 157929
 2012-06-04 14:02:08 +00:00
Chris Lattner
68489fe6b7 remove an unused variable. 
llvm-svn: 157872
 2012-06-02 01:03:42 +00:00
Akira Hatanaka
334dbca66f Set operation actions for load/store nodes in the Mips backend. 
llvm-svn: 157866
 2012-06-02 00:04:42 +00:00
Akira Hatanaka
b7342fea3a Define functions MipsTargetLowering::LowerLOAD and LowerSTORE which 
custom-lower unaligned load and store nodes.

llvm-svn: 157864
 2012-06-02 00:03:49 +00:00
Akira Hatanaka
80b29cb00a Define Mips specific unaligned load/store nodes. 
llvm-svn: 157863
 2012-06-02 00:03:12 +00:00
Akira Hatanaka
23e92c0ddb Expand unaligned i16 loads/stores for the Mips backend. 
This is the first of a series of patches which make changes to the backend to
emit unaligned load/store instructions (lwl,lwr,swl,swr) during instruction
selection.

llvm-svn: 157862
 2012-06-02 00:02:45 +00:00
Akira Hatanaka
9d64361208 Cleanup and factoring of mips16 tablegen classes. Make register classes 
CPU16RegsRegClass and CPURARegRegClass available. Add definition of mips16
jalr instruction.

Patch by Reed Kotler.

llvm-svn: 157730
 2012-05-31 02:59:44 +00:00
Justin Holewinski
77c4679dae Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCall 
to pass around a struct instead of a large set of individual values.  This
cleans up the interface and allows more information to be added to the struct
for future targets without requiring changes to each and every target.

NV_CONTRIB

llvm-svn: 157479
 2012-05-25 16:35:28 +00:00
Akira Hatanaka
ae43b7da61 Make the following changes in MipsISelLowering.cpp: 
- Stop creating stack frame objects needed for saving $gp.
- Insert a node that copies the global pointer register to register $gp
  before the call node. This will ensure $gp is valid at the entry of the
  called function.

llvm-svn: 156692
 2012-05-12 03:19:04 +00:00
Akira Hatanaka
bd2f3d1c46 Expand 64-bit shifts if target ABI is O32. 
llvm-svn: 156457
 2012-05-09 00:55:21 +00:00
Eric Christopher
c2cd5bdf83 Add support for the 'x' constraint. 
Patch by Jack Carter.

llvm-svn: 156295
 2012-05-07 06:25:19 +00:00
Eric Christopher
87e8163c57 Add support for the 'l' constraint. 
Patch by Jack Carter.

llvm-svn: 156294
 2012-05-07 06:25:15 +00:00
Eric Christopher
af8eabbbd8 Add support for the 'c' constraint. 
Patch by Jack Carter.

llvm-svn: 156293
 2012-05-07 06:25:10 +00:00
Eric Christopher
0f1a0afa75 Add support for the 'P' constraint. 
Patch by Jack Carter.

llvm-svn: 156292
 2012-05-07 06:25:02 +00:00
Eric Christopher
a6552ba637 Add support for the 'O' constraint. 
Patch by Jack Carter.

llvm-svn: 156285
 2012-05-07 05:46:48 +00:00
Eric Christopher
5e1efebf09 Add support for the 'N' inline asm constraint. 
Patch by Jack Carter.

llvm-svn: 156284
 2012-05-07 05:46:43 +00:00
Eric Christopher
e5a46b70b3 Add support for the 'L' inline asm constraint. 
Patch by Jack Carter.

llvm-svn: 156283
 2012-05-07 05:46:37 +00:00
Eric Christopher
267aa256cb Add support for the inline asm constraint 'K'. 
llvm-svn: 156282
 2012-05-07 05:46:29 +00:00
Eric Christopher
bf784be9ae Support the 'J' constraint. 
Patch by Jack Carter.

llvm-svn: 156280
 2012-05-07 03:13:42 +00:00
Eric Christopher
929ba63dcf Add support for the 'I' inline asm constraint. Also add tests 
from the previous 2 patches.

Patch by Jack Carter.

llvm-svn: 156279
 2012-05-07 03:13:32 +00:00
Eric Christopher
0c140afa87 Allow 64 bit integer values in gpu registers if arch and abi are 64 bit. 
Patch by Jack Carter.

llvm-svn: 156278
 2012-05-07 03:13:22 +00:00
Eric Christopher
6397520b96 When using inline asm constraints representing 
non-floating point general registers allow 8 and 16-bit
elements.

Patch by Jack Carter.

llvm-svn: 156277
 2012-05-07 03:13:16 +00:00
Hans Wennborg
b3c41d012d Make ARM and Mips use TargetMachine::getTLSModel() 
This moves the logic for selecting a TLS model to a single place,
instead of the previous three (ARM, Mips, and X86 which already
uses this function).

llvm-svn: 156162
 2012-05-04 09:40:39 +00:00
NAKAMURA Takumi
a5df77be2f llvm/lib/Target: [PR12611] Add "llvm/Support/raw_ostream.h" for Debug build on MSVC. 
Thanks to Andy Gibbs, to report the issue.

llvm-svn: 155287
 2012-04-21 15:31:45 +00:00
Craig Topper
90d95a9142 Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent. 
llvm-svn: 155188
 2012-04-20 07:30:17 +00:00
Akira Hatanaka
48dbb62cb1 Emit neg.s or neg.d only if -enable-no-nans-fp-math is supplied by user, 
otherwise expand FNEG during legalization.

llvm-svn: 154546
 2012-04-11 22:59:08 +00:00
Akira Hatanaka
11a442d515 Emit abs.s or abs.d only if -enable-no-nans-fp-math is supplied by user. 
Invalid operation is signaled if the operand of these instructions is NaN.

llvm-svn: 154545
 2012-04-11 22:49:04 +00:00
Akira Hatanaka
6636922675 Fix bugs in lowering of FCOPYSIGN nodes. 
- FCOPYSIGN nodes that have operands of different types were not handled.
- Different code was generated depending on the endianness of the target.

Additionally, code is added that emits INS and EXT instructions, if they are
supported by target (they are R2 instructions).

llvm-svn: 154540
 2012-04-11 22:13:04 +00:00
Akira Hatanaka
e5ea70212f Reapply 154038 without the failing test. 
llvm-svn: 154062
 2012-04-04 22:16:36 +00:00
Owen Anderson
f6f930a990 Revert r154038. It was causing make check failures. 
llvm-svn: 154054
 2012-04-04 21:18:58 +00:00