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175 Commits

Author SHA1 Message Date
Rafael Espindola
d15cd32b9f Remove the linker_private and linker_private_weak linkages.
These linkages were introduced some time ago, but it was never very
clear what exactly their semantics were or what they should be used
for. Some investigation found these uses:

* utf-16 strings in clang.
* non-unnamed_addr strings produced by the sanitizers.

It turns out they were just working around a more fundamental problem.
For some sections a MachO linker needs a symbol in order to split the
section into atoms, and llvm had no idea that was the case. I fixed
that in r201700 and it is now safe to use the private linkage. When
the object ends up in a section that requires symbols, llvm will use a
'l' prefix instead of a 'L' prefix and things just work.

With that, these linkages were already dead, but there was a potential
future user in the objc metadata information. I am still looking at
CGObjcMac.cpp, but at this point I am convinced that linker_private
and linker_private_weak are not what they need.

The objc uses are currently split in

* Regular symbols (no '\01' prefix). LLVM already directly provides
whatever semantics they need.
* Uses of a private name (start with "\01L" or "\01l") and private
linkage. We can drop the "\01L" and "\01l" prefixes as soon as llvm
agrees with clang on L being ok or not for a given section. I have two
patches in code review for this.
* Uses of private name and weak linkage.

The last case is the one that one could think would fit one of these
linkages. That is not the case. The semantics are

* the linker will merge these symbol by *name*.
* the linker will hide them in the final DSO.

Given that the merging is done by name, any of the private (or
internal) linkages would be a bad match. They allow llvm to rename the
symbols, and that is really not what we want. From the llvm point of
view, these objects should really be (linkonce|weak)(_odr)?.

For now, just keeping the "\01l" prefix is probably the best for these
symbols. If we one day want to have a more direct support in llvm,
IMHO what we should add is not a linkage, it is just a hidden_symbol
attribute. It would be applicable to multiple linkages. For example,
on weak it would produce the current behavior we have for objc
metadata. On internal, it would be equivalent to private (and we
should then remove private).

llvm-svn: 203866
2014-03-13 23:18:37 +00:00
Tim Northover
68c567a38a IR: add a second ordering operand to cmpxhg for failure
The syntax for "cmpxchg" should now look something like:

	cmpxchg i32* %addr, i32 42, i32 3 acquire monotonic

where the second ordering argument gives the required semantics in the case
that no exchange takes place. It should be no stronger than the first ordering
constraint and cannot be either "release" or "acq_rel" (since no store will
have taken place).

rdar://problem/15996804

llvm-svn: 203559
2014-03-11 10:48:52 +00:00
Venkatraman Govindaraju
789e2fd1b7 [Sparc] Add support for parsing directives in SparcAsmParser.
llvm-svn: 202564
2014-03-01 02:18:04 +00:00
Venkatraman Govindaraju
439a7d90a6 [Sparc] Emit 'restore' instead of 'restore %g0, %g0, %g0'. This improves the readability of the generated code.
llvm-svn: 202563
2014-03-01 01:04:26 +00:00
Roman Divacky
f36febf578 Lower FNEG just like FABS to fneg[ds] and fmov[ds], thus avoiding
expensive libcall. Also, Qp_neg is not implemented on at least
FreeBSD. This is also what gcc is doing.

llvm-svn: 202422
2014-02-27 19:26:29 +00:00
Benjamin Kramer
bb5b968592 SPARC: Implement TRAP lowering. Matches what GCC emits.
llvm-svn: 201994
2014-02-23 21:43:52 +00:00
Roman Divacky
1a91fd1bdc Expand 64bit {SHL,SHR,SRA}_PARTS on sparcv9.
llvm-svn: 201718
2014-02-19 21:35:39 +00:00
Venkatraman Govindaraju
2661a3f234 [Sparc] Remove spurious checks from a testcase.
llvm-svn: 201690
2014-02-19 15:57:49 +00:00
Daniel Sanders
7a3a160940 Re-commit: Demote EmitRawText call in AsmPrinter::EmitInlineAsm() and remove hasRawTextSupport() call
Summary:
AsmPrinter::EmitInlineAsm() will no longer use the EmitRawText() call for
targets with mature MC support. Such targets will always parse the inline
assembly (even when emitting assembly). Targets without mature MC support
continue to use EmitRawText() for assembly output.

The hasRawTextSupport() check in AsmPrinter::EmitInlineAsm() has been replaced
with MCAsmInfo::UseIntegratedAs which when true, causes the integrated assembler
to parse inline assembly (even when emitting assembly output). UseIntegratedAs
is set to true for targets that consider any failure to parse valid assembly
to be a bug. Target specific subclasses generally enable the integrated
assembler in their constructor. The default value can be overridden with
-no-integrated-as.

All tests that rely on inline assembly supporting invalid assembly (for example,
those that use mnemonics such as 'foo' or 'hello world') have been updated to
disable the integrated assembler.

Changes since review (and last commit attempt):
- Fixed test failures that were missed due to configuration of local build.
  (fixes crash.ll and a couple others).
- Fixed tests that happened to pass because the local build was on X86
  (should fix 2007-12-17-InvokeAsm.ll)
- mature-mc-support.ll's should no longer require all targets to be compiled.
  (should fix ARM and PPC buildbots)
- Object output (-filetype=obj and similar) now forces the integrated assembler
  to be enabled regardless of default setting or -no-integrated-as.
  (should fix SystemZ buildbots)

Reviewers: rafael

Reviewed By: rafael

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D2686

llvm-svn: 201333
2014-02-13 14:44:26 +00:00
Venkatraman Govindaraju
b475c5619b [Sparc] Emit relocations for Thread Local Storage (TLS) when integrated assembler is used.
llvm-svn: 200962
2014-02-07 05:54:20 +00:00
Venkatraman Govindaraju
3eb62616b0 [Sparc] Emit correct relocations for PIC code when integrated assembler is used.
llvm-svn: 200961
2014-02-07 04:24:35 +00:00
Venkatraman Govindaraju
9c2c79ab67 [Sparc] Set %o7 as the return address register instead of %i7 in MCRegisterInfo. Also, add CFI instructions to initialize the frame correctly.
llvm-svn: 200617
2014-02-01 18:54:16 +00:00
Jakob Stoklund Olesen
412a5b3d9b Implement SPARCv9 atomic_swap_64 with a pseudo.
The SWAP instruction only exists in a 32-bit variant, but the 64-bit
atomic swap can be implemented in terms of CASX, like the other atomic
rmw primitives.

llvm-svn: 200453
2014-01-30 04:48:46 +00:00
Venkatraman Govindaraju
a50ca1f645 [Sparc] Use %r_disp32 for pc_rel entries in FDE as well.
This makes MCAsmInfo::getExprForFDESymbol() a virtual function and overrides it in SparcMCAsmInfo.

llvm-svn: 200376
2014-01-29 06:59:20 +00:00
Venkatraman Govindaraju
1541483555 [Sparc] Use %r_disp32 for pc_rel entries in gcc_except_table and eh_frame.
Otherwise, assembler (gas) fails to assemble them with error message "operation
combines symbols in different segments". This is because MC computes
pc_rel entries with subtract expression between labels from different sections.

llvm-svn: 200373
2014-01-29 04:51:35 +00:00
Venkatraman Govindaraju
416f0c2389 [SparcV9] Use correct register class (I64RegClass) to hold the address of _GLOBAL_OFFSET_TABLE_ in sparcv9.
llvm-svn: 200368
2014-01-29 03:35:08 +00:00
Jakob Stoklund Olesen
8a060724b3 Fix the DWARF EH encodings for Sparc PIC code.
Also emit the stubs that were generated for references to typeinfo
symbols.

llvm-svn: 200282
2014-01-28 02:52:26 +00:00
Jakob Stoklund Olesen
8dcf39e4f3 Clean up the Legal/Expand logic for SPARC popc.
llvm-svn: 200141
2014-01-26 08:12:34 +00:00
Jakob Stoklund Olesen
6804208a8e Only generate the popc instruction for SPARC CPUs that implement it.
The popc instruction is defined in the SPARCv9 instruction set
architecture, but it was emulated on CPUs older than Niagara 2.

llvm-svn: 200131
2014-01-26 06:09:59 +00:00
Jakob Stoklund Olesen
0e9b704ac9 Fix swapped CASA operands.
Found by SingleSource/UnitTests/AtomicOps.c

llvm-svn: 200130
2014-01-26 06:09:54 +00:00
Jakob Stoklund Olesen
95b427580f Implement atomicrmw operations in 32 and 64 bits for SPARCv9.
These all use the compare-and-swap CASA/CASXA instructions.

llvm-svn: 199975
2014-01-24 06:23:31 +00:00
Venkatraman Govindaraju
2dcfaac1b8 [Sparc] Add support for inline assembly constraints which specify registers by their aliases.
llvm-svn: 199786
2014-01-22 03:18:42 +00:00
Venkatraman Govindaraju
6c498f0e2f [Sparc] Add support for inline assembly constraint 'I'.
llvm-svn: 199781
2014-01-22 01:29:51 +00:00
Venkatraman Govindaraju
0a2da12ffd [Sparc] Do not add PC to _GLOBAL_OFFSET_TABLE_ address to access GOT in absolute code.
Fixes PR#18521

llvm-svn: 199775
2014-01-22 00:13:18 +00:00
Jakob Stoklund Olesen
45496cea60 Always let value types influence register classes.
When creating a virtual register for a def, the value type should be
used to pick the register class. If we only use the register class
constraint on the instruction, we might pick a too large register class.

Some registers can store values of different sizes. For example, the x86
xmm registers can hold f32, f64, and 128-bit vectors. The three
different value sizes are represented by register classes with identical
register sets: FR32, FR64, and VR128. These register classes have
different spill slot sizes, so it is important to use the right one.

The register class constraint on an instruction doesn't necessarily care
about the size of the value its defining. The value type determines
that.

This fixes a problem where InstrEmitter was picking 32-bit register
classes for 64-bit values on SPARC.

llvm-svn: 199187
2014-01-14 06:18:38 +00:00
Jakob Stoklund Olesen
026885712c Handle bundled terminators in isBlockOnlyReachableByFallthrough.
Targets like SPARC and MIPS have delay slots and normally bundle the
delay slot instruction with the corresponding terminator.

Teach isBlockOnlyReachableByFallthrough to find any MBB operands on
bundled terminators so SPARC doesn't need to specialize this function.

llvm-svn: 199061
2014-01-12 19:24:08 +00:00
Jakob Stoklund Olesen
3dd52f1fbd The SPARCv9 ABI returns a float in %f0.
This is different from the argument passing convention which puts the
first float argument in %f1.

With this patch, all returned floats are treated as if the 'inreg' flag
were set. This means multiple float return values get packed in %f0,
%f1, %f2, ...

Note that when returning a struct in registers, clang will set the
'inreg' flag on the return value, so that behavior is unchanged. This
also happens when returning a float _Complex.

llvm-svn: 199028
2014-01-12 04:13:17 +00:00
Venkatraman Govindaraju
406e85c8e3 [Sparc] Add missing processor types: v7 and niagara
llvm-svn: 199024
2014-01-11 23:56:13 +00:00
Benjamin Kramer
002aed9cb3 Fix broken CHECK lines.
llvm-svn: 199016
2014-01-11 21:06:00 +00:00
Venkatraman Govindaraju
db6b1cbac8 [Sparc] Bundle instruction with delay slow and its filler. Now, we can use -verify-machineinstrs with SPARC backend.
llvm-svn: 199014
2014-01-11 19:38:03 +00:00
Venkatraman Govindaraju
b0841deda2 [Sparc] Emit retl/ret instead of jmp instruction. It improves the readability of the assembly generated.
llvm-svn: 198910
2014-01-10 02:55:27 +00:00
Venkatraman Govindaraju
bfcef24b91 [SparcV9]: Implement RETURNADDR and FRAMEADDR lowering in SPARC64.
Fixes PR18356.

llvm-svn: 198480
2014-01-04 07:17:21 +00:00
Venkatraman Govindaraju
cb22135b23 [Sparc] Handle atomic loads/stores in sparc backend.
llvm-svn: 198286
2014-01-01 22:11:54 +00:00
Venkatraman Govindaraju
e8745ffca1 [SparcV9]: Custom lower UMULO/SMULO so that the arguments are send to __multi3() in correct order.
llvm-svn: 198281
2014-01-01 20:22:45 +00:00
Venkatraman Govindaraju
2fc6090f42 [SparcV9]: Use SRL instead of SLL to clear top 32-bits in ctpop:i32. SLL does not clear top 32 bit, only SRL does.
llvm-svn: 198280
2014-01-01 19:00:10 +00:00
Venkatraman Govindaraju
451c278cbc [SparcV9] Use separate instruction patterns for 64 bit arithmetic instructions instead of reusing 32 bit instruction patterns.
This is done to avoid spilling the result of the 64-bit instructions to a 4-byte slot.

llvm-svn: 198157
2013-12-29 07:15:09 +00:00
Venkatraman Govindaraju
d46a491054 [SparcV9] For codegen generated library calls that return float, set inreg flag manually in LowerCall().
This makes the sparc backend to generate Sparc64 ABI compliant code.

llvm-svn: 198149
2013-12-29 04:27:21 +00:00
Venkatraman Govindaraju
05510dd426 [SparcV9]: Implement lowering of long double (fp128) arguments in Sparc64 ABI.
Also, pass fp128 arguments to varargs through integer registers if necessary.

llvm-svn: 198145
2013-12-29 01:20:36 +00:00
Venkatraman Govindaraju
8c2d10768d [Sparc] Lower and MachineInstr to MC and print assembly using MCInstPrinter.
llvm-svn: 198030
2013-12-26 01:49:59 +00:00
Venkatraman Govindaraju
700f24667b [SPARCV9]: Adjust the resultant pointer of DYNAMIC_STACKALLOC with the stack BIAS on sparcV9.
llvm-svn: 196755
2013-12-09 05:13:25 +00:00
Venkatraman Govindaraju
c918055fdb [Sparc]: Implement getSetCCResultType() in SparcTargetLowering so that umulo/smulo can be lowered on sparcv9 without an assertion error.
llvm-svn: 196751
2013-12-09 04:02:15 +00:00
Venkatraman Govindaraju
0ab9fc8dbd [SparcV9]: Expand MULHU/MULHS:i64 and UMUL_LOHI/SMUL_LOHI:i64 on sparcv9.
This fixes PR18150.

llvm-svn: 196735
2013-12-08 22:06:07 +00:00
Venkatraman Govindaraju
d0d03fae95 [Sparc] Emit large negative adjustments to SP/FP with sethi+xor instead of sethi+or. This generates correct code for both sparc32 and sparc64.
llvm-svn: 195576
2013-11-24 20:23:25 +00:00
Venkatraman Govindaraju
73dd53211d [SparcV9]: Do not emit .register directives for global registers that are clobbered by calls but not used in the function itself.
llvm-svn: 195574
2013-11-24 18:41:49 +00:00
Venkatraman Govindaraju
0c27a5ac2c [SparcV9] Enable custom lowering of DYNAMIC_STACKALLOC in sparc64.
llvm-svn: 195573
2013-11-24 17:41:41 +00:00
Venkatraman Govindaraju
8ce290e5fa [SparcV9] Handle i64 <-> float conversions in sparcv9 mode.
llvm-svn: 193957
2013-11-03 12:28:40 +00:00
Venkatraman Govindaraju
1b0f7d035d [Sparc] Expand FP_TO_UINT, UINT_TO_FP for fp128.
llvm-svn: 193947
2013-11-03 08:00:19 +00:00
Venkatraman Govindaraju
c60684ae6f [SparcV9] Add ctpop instruction for i64. Also, expand ctlz, cttz and bswap.
llvm-svn: 193941
2013-11-03 05:59:07 +00:00
Roman Divacky
e5df4dcd13 SparcV9 doesnt have rem instruction either.
llvm-svn: 193789
2013-10-31 19:22:33 +00:00
Venkatraman Govindaraju
aedc12be2e [Sparc] Disable tail call optimization for sparc64.
This patch fixes PR17506.

llvm-svn: 192294
2013-10-09 12:50:39 +00:00