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420 Commits

Author SHA1 Message Date
Jim Grosbach
d4e9b9844d ARM assembly parsing and encoding test for BKPT. 
llvm-svn: 137898
 2011-08-17 23:11:13 +00:00
Jim Grosbach
fefc732dd9 ARM assembly parsing and encoding test for BIC. 
llvm-svn: 137895
 2011-08-17 23:00:53 +00:00
Jim Grosbach
b0e8cd2bfa Thumb assembly parsing and encoding for B. 
llvm-svn: 137891
 2011-08-17 22:57:40 +00:00
Jim Grosbach
1b761bd2d5 Thumb assembly parsing and encoding for ASR. 
llvm-svn: 137889
 2011-08-17 22:49:09 +00:00
Jim Grosbach
0115c6f75b Thumb assembly parsing and encoding for ADR. 
llvm-svn: 137864
 2011-08-17 20:37:40 +00:00
Jim Grosbach
20329b9f8e Add a couple of FIXMEs. 
llvm-svn: 137861
 2011-08-17 20:35:57 +00:00
Jim Grosbach
39af673350 Thumb assembly parsing and encoding for ADC(register) instruction. 
llvm-svn: 137833
 2011-08-17 17:55:28 +00:00
Jim Grosbach
c93201cb25 Add missing '@' delimiter. 
llvm-svn: 137832
 2011-08-17 17:46:01 +00:00
Jim Grosbach
ae9f7f938f Thumb ADD(immediate) parsing support. 
llvm-svn: 137788
 2011-08-16 23:57:34 +00:00
Jim Grosbach
7a5c6948ca Thumb parsing diagnostics for low-reg requirements on ADD and MOV. 
llvm-svn: 137779
 2011-08-16 22:20:01 +00:00
Jim Grosbach
850f937ecc Thumb assembly parsing and encoding for ADD(register) instruction. 
llvm-svn: 137759
 2011-08-16 21:34:08 +00:00
Jim Grosbach
192f298228 Add testcase for r137746. 
llvm-svn: 137754
 2011-08-16 21:11:21 +00:00
Jim Grosbach
06f3a3b427 Tidy up formatting. 
llvm-svn: 137747
 2011-08-16 20:55:41 +00:00
Jim Grosbach
8d67a0e07c ARM thumb assembly parsing for arithmetic flag setting instructions. 
Thumb one requires that many arithmetic instruction forms have an 'S'
suffix. For Thumb2, the whether the suffix is required or precluded depends
on whether the instruction is in an IT block. Use target parser predicates
to check for these sorts of context-sensitive constraints.

llvm-svn: 137746
 2011-08-16 20:45:50 +00:00
Jim Grosbach
90387c44f4 ARM .align NOP padding uses different encoding pre-ARMv6. 
Patch by Kristof Beyls and James Malloy.

llvm-svn: 137723
 2011-08-16 17:06:20 +00:00
Owen Anderson
4854258d9c Fix incorrect encoding of UMAAL and friends. Patch by James Molloy. 
llvm-svn: 137641
 2011-08-15 20:08:25 +00:00
Jim Grosbach
d154fc4c8f Tidy up formatting. 
llvm-svn: 137471
 2011-08-12 17:43:31 +00:00
Jim Grosbach
1cfe8c24d5 Tidy up formatting. 
llvm-svn: 137464
 2011-08-12 17:01:02 +00:00
Jim Grosbach
ade39d38e1 Clean up formatting a bit. 
llvm-svn: 137393
 2011-08-11 23:57:17 +00:00
Jim Grosbach
d17df06881 ARM vector compare to zero instruction assembly parsing support. 
llvm-svn: 137389
 2011-08-11 23:51:13 +00:00
Jim Grosbach
41ef68eb17 Fix tests per now-correct encoding as of r137371. 
llvm-svn: 137376
 2011-08-11 22:31:48 +00:00
Jim Grosbach
edefbb31c3 ARM STRT assembly parsing and encoding. 
llvm-svn: 137372
 2011-08-11 22:18:00 +00:00
Jim Grosbach
ed8a320007 ARM load shifted register pre-index fix shift value asm parser encoding. 
llvm-svn: 137367
 2011-08-11 22:05:09 +00:00
Jim Grosbach
609316e481 ARM STRHT assembly parsing and encoding. 
llvm-svn: 137358
 2011-08-11 21:39:41 +00:00
Jim Grosbach
5c12d41c95 ARM STRH assembly parsing and encoding. 
llvm-svn: 137353
 2011-08-11 21:17:22 +00:00
Jim Grosbach
81b2835f83 ARM STRD assembly parsing and encoding. 
llvm-svn: 137342
 2011-08-11 20:28:23 +00:00
Jim Grosbach
bfc85134c2 ARM STRBT assembly parsing and encoding. 
llvm-svn: 137337
 2011-08-11 20:04:56 +00:00
Jim Grosbach
87f0f921b5 Add FIXME. 
llvm-svn: 137336
 2011-08-11 19:43:42 +00:00
Jim Grosbach
a6572a1201 ARM STRB assembly parsing and encoding tests. 
llvm-svn: 137335
 2011-08-11 19:42:58 +00:00
Jim Grosbach
9673dc9e01 Fix a copy/paste error so that LDRB(register) actually gets tested. 
llvm-svn: 137333
 2011-08-11 19:34:23 +00:00
Jim Grosbach
986a3eb0b2 ARM STR(register) assembly parsing and encoding tests. 
llvm-svn: 137332
 2011-08-11 19:26:17 +00:00
Jim Grosbach
e6bd3a1ab8 ARM STR(immediate) assembly parsing and encoding. 
llvm-svn: 137331
 2011-08-11 19:22:40 +00:00
Jim Grosbach
9717a9c0d3 ARM push of a single register encodes as pre-indexed STR. 
Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.

llvm-svn: 137318
 2011-08-11 18:07:11 +00:00
Jim Grosbach
abaaf4513f ARM pop of a single register encodes as post-indexed LDR. 
Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.

llvm-svn: 137316
 2011-08-11 17:35:48 +00:00
Jim Grosbach
eb96dd6c99 ARM tests for LDRSHT assembly parsing and encoding. 
llvm-svn: 137274
 2011-08-10 23:18:30 +00:00
Jim Grosbach
e2cc6866d1 ARM tests for LDRSH assembly parsing and encoding. 
llvm-svn: 137272
 2011-08-10 23:12:25 +00:00
Jim Grosbach
f65a625648 ARM tests for LDRSBT assembly parsing and encoding. 
llvm-svn: 137271
 2011-08-10 23:08:56 +00:00
Jim Grosbach
e22ad37645 ARM tests for LDRSB assembly parsing and encoding. 
llvm-svn: 137270
 2011-08-10 23:06:44 +00:00
Jim Grosbach
f291232aa1 Add FIXME. 
llvm-svn: 137265
 2011-08-10 22:56:43 +00:00
Jim Grosbach
5c5f1c8305 ARM tests for LDRHT assembly parsing and encoding. 
llvm-svn: 137263
 2011-08-10 22:55:38 +00:00
Jim Grosbach
7c1596bf26 ARM tests for LDRH(register) assembly parsing and encoding. 
llvm-svn: 137261
 2011-08-10 22:45:42 +00:00
Jim Grosbach
e0ccd6b34e ARM LDRH(immediate) assembly parsing and encoding support. 
llvm-svn: 137260
 2011-08-10 22:42:16 +00:00
Jim Grosbach
e0c10a6d0c Add FIXME 
llvm-svn: 137258
 2011-08-10 22:20:38 +00:00
Jim Grosbach
4ad2dc8bb2 ARM LDRD(register) assembly parsing and encoding. 
Add support for literal encoding of #-0 along the way.

llvm-svn: 137254
 2011-08-10 21:56:18 +00:00
Jim Grosbach
bbef0044c8 ARM LDRD(immediate) assembly parsing and encoding support. 
llvm-svn: 137244
 2011-08-10 20:29:19 +00:00
Jim Grosbach
d6da18cf19 ARM parsing and encoding for LDRBT instruction. 
Fix the instruction representation to correctly only allow post-indexed form.
Add tests.

llvm-svn: 137074
 2011-08-08 23:28:47 +00:00
Jim Grosbach
dce26073db ARM parsing and encoding for LDRB instruction. 
llvm-svn: 137071
 2011-08-08 22:37:06 +00:00
Jim Grosbach
1dbe50798e Add FIXME. 
llvm-svn: 137070
 2011-08-08 22:11:33 +00:00
Jim Grosbach
00c4316907 ARM load instruction shifted register index operands. 
Parsing and encoding for shifted index operands for load instructions.

llvm-svn: 136986
 2011-08-05 22:03:36 +00:00
Jim Grosbach
40a7e379c4 ARM indexed load assembly parsing and encoding. 
More parsing support for indexed loads. Fix pre-indexed with writeback
parsing for register offsets and handle basic post-indexed offsets.

llvm-svn: 136982
 2011-08-05 21:28:30 +00:00