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Commit Graph

154715 Commits

Author SHA1 Message Date
Craig Topper
26afdb807c [X86] Make sure we still mark the full register as implicitly defined when we shrink 256/512 bit zeroing xors to 128-bit.
Not sure if anything really cares, but this seems like the right thing to do.

llvm-svn: 314071
2017-09-24 05:24:51 +00:00
Dylan McKay
2f7c470cc7 [AVR] Implement getCmpLibcallReturnType().
This fixes the avr-rust issue (#75) with floating-point comparisons generating broken code.
By default, LLVM assumes these comparisons return 32-bit values, but ours are 8-bit.

Patch By Thomas Backman.

llvm-svn: 314070
2017-09-24 01:07:26 +00:00
Davide Italiano
e1060417c3 [Verifier] Stop accepting broken DIGlobalVariable(s).
The code wasn't yelling at the user when there's a reference
from a DIGlobalVariableExpression. Thanks to Adrian for the
reduced testcase. Fixes PR34672.

llvm-svn: 314069
2017-09-24 01:06:35 +00:00
Simon Pilgrim
60b112db3a [X86] Regenerate i64 to v2f32 bitcast test
llvm-svn: 314068
2017-09-23 19:18:29 +00:00
Sanjay Patel
8fe52dcc51 [x86] reduce 64-bit mask constant to 32-bits by right shifting
This is a follow-up from D38181 (r314023). We have to put 64-bit
constants into a register using a separate instruction, so we
should try harder to avoid that.

From what I see, we're not likely to encounter this pattern in the 
DAG because the upstream setcc combines from this don't (usually?) 
produce this pattern. If we fix that, then this will become more 
relevant. Since the cost of handling this case is just loosening 
the predicate of the existing fold, we might as well do it now.

llvm-svn: 314064
2017-09-23 14:32:07 +00:00
Sanjay Patel
47c506979b [x86] add an add+shift test for follow-up suggestion from D38181; NFC
llvm-svn: 314063
2017-09-23 14:24:07 +00:00
Nemanja Ivanovic
468e2da8ae [PowerPC] Eliminate compares - add i32 sext/zext handling for SETULT/SETUGT
As mentioned in https://reviews.llvm.org/D33718, this simply adds another
pattern to the compare elimination sequence and is committed without a
differential revision.

llvm-svn: 314062
2017-09-23 12:53:03 +00:00
Nemanja Ivanovic
ce5d3e6fbd [PowerPC] Eliminate compares - add i32 sext/zext handling for SETULE/SETUGE
As mentioned in https://reviews.llvm.org/D33718, this simply adds another
pattern to the compare elimination sequence and is committed without a
differential revision.

llvm-svn: 314060
2017-09-23 09:50:12 +00:00
Craig Topper
58c912b755 [X86] Move the getInsertVINSERTImmediate and getExtractVEXTRACTImmediate helper functions over to X86ISelDAGToDAG.cpp
Redefine them to call getI8Imm and return that directly.

llvm-svn: 314059
2017-09-23 05:34:07 +00:00
Craig Topper
709e147eaa [X86] Remove is the isVINSERT*Index/isVEXTRACT*Index predicates from isel.
The only insert_subvector/extract_subvector nodes that make it to isel are guaranteed to match.

llvm-svn: 314058
2017-09-23 05:34:06 +00:00
Nemanja Ivanovic
118a68dea9 [PowerPC] Eliminate compares - add i32 sext/zext handling for SETLT/SETGT
As mentioned in https://reviews.llvm.org/D33718, this simply adds another
pattern to the compare elimination sequence and is committed without a
differential revision.

llvm-svn: 314055
2017-09-23 04:41:34 +00:00
Reid Kleckner
7f2317ba9c Commit missing fixes for tool_file_rename
llvm-svn: 314051
2017-09-23 01:04:42 +00:00
Reid Kleckner
e0df0bbd27 [Support] Rename tool_output_file to ToolOutputFile, NFC
This class isn't similar to anything from the STL, so it shouldn't use
the STL naming conventions.

llvm-svn: 314050
2017-09-23 01:03:17 +00:00
Eugene Zelenko
012d4e61ae [CodeGen] Fix build bots which uses old Clang broken in r314046. (NFC)
llvm-svn: 314049
2017-09-22 23:55:32 +00:00
Eugene Zelenko
337f4a4f6d [CodeGen] Fix some Clang-tidy modernize-use-default-member-init and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 314046
2017-09-22 23:46:57 +00:00
Konstantin Belochapka
96e1c71c44 [X86] [MC] fixed non optimal encoding of instruction memory operand (PR24038).
Fixed suboptimal encoding of instruction memory operand when assembler is used to select 32 bit fixup rather than 8 bit immediate for encoding memory offset value.
Differential Revision: https://reviews.llvm.org/D38117

llvm-svn: 314044
2017-09-22 23:37:48 +00:00
Reid Kleckner
3f2896dda9 Fix uninteneded fallthrough detected by GCC warning
llvm-svn: 314043
2017-09-22 23:19:52 +00:00
Craig Topper
b01d5413e4 [InstCombine] Teach foldICmpUsingKnownBits to simplify SLE/SGE/ULE/UGE to equality comparisons when the min/max ranges intersect in a single value.
This is the inverse of what we do for SGT/SLT/UGT/ULT.

llvm-svn: 314032
2017-09-22 21:47:22 +00:00
Craig Topper
fb5f5f7b5b [InstCombine] Add test cases for known bits simplifications for comparisons that don't depend on constant RHS. NFC
This shows some missing simplifications for sge/sle/uge/ule relative to their non-equality counterparts.

llvm-svn: 314031
2017-09-22 21:47:21 +00:00
Craig Topper
7889014853 [InstCombine] Remove a FIXME from a test that was fixed in r314025.
llvm-svn: 314030
2017-09-22 21:47:20 +00:00
Ilya Biryukov
327dbdbacc Fixed broken links in docs.
Replaced references to `llvm.org/klaus` with `git.llvm.org/klaus`.

llvm-svn: 314028
2017-09-22 21:10:37 +00:00
Sanjay Patel
a0ebd7c32a [x86] remove over-specified platform from test config
llvm-svn: 314027
2017-09-22 21:07:13 +00:00
Stefan Pintilie
025429eb69 [PowerPC] Mark P9 scheduling model complete
This patch just adds the missing information to the P9 scheduling model to allow
the model to be marked as complete.

The model has been verified against P9 documentation. The model was verified
with utils/schedcover.py.

Differential Revision: https://reviews.llvm.org/D35695

llvm-svn: 314026
2017-09-22 20:17:25 +00:00
Craig Topper
a151e88501 [InstCombine] Add constant splat handling to one of the ICMP_SLT/SGT cases in foldICmpUsingKnownBits.
llvm-svn: 314025
2017-09-22 19:54:15 +00:00
Sanjay Patel
9b9148c039 [x86] shiftRightAlgebraic -> shiftRightArithmetic; NFC
x86 re-education camp is in session. The LLVM LangRef agrees with x86 too.
The DAG nodes are undocumented and ambiguous as always. :)

llvm-svn: 314024
2017-09-22 19:49:37 +00:00
Sanjay Patel
d30aaf33b0 [x86] swap order of srl (and X, C1), C2 when it saves size
The (non-)obvious win comes from saving 3 bytes by using the 0x83 'and' opcode variant instead of 0x81. 
There are also better improvements based on known-bits that allow us to eliminate the mask entirely.

As noted, this could be extended. There are potentially other wins from always shifting first, but doing
that reveals a tangle of problems in other pattern matching. We do this transform generically in 
instcombine, but we often have icmp IR that doesn't match that pattern, so we must account for this
in the backend.

Differential Revision: https://reviews.llvm.org/D38181

llvm-svn: 314023
2017-09-22 19:37:21 +00:00
Craig Topper
9d5fb1b5c3 [InstCombine] Move the call to isSignBitCheck into getDemandedBitsLHSMask instead of calling it outside and passing its result through a flag. NFCI
The result of the isSignBitCheck isn't used anywhere else and this allows us to share the m_APInt call in the likely case that it isn't a sign bit check.

llvm-svn: 314018
2017-09-22 18:57:23 +00:00
Craig Topper
7e37824b8f [InstCombine] Simplify check for RHS being a splat constant in foldICmpUsingKnownBits by just checking Op1Min==Op1Max rather than going through m_APInt.
llvm-svn: 314017
2017-09-22 18:57:22 +00:00
Craig Topper
ef284eb207 [InstCombine] Make cases for ICMP_UGT/ICMP_ULT use similar formatting since they use similar code. NFC
llvm-svn: 314016
2017-09-22 18:57:20 +00:00
Rafael Espindola
4755a700ba Move code to a helper function. NFC.
Part of a patch by Jake Ehrlich!

llvm-svn: 314012
2017-09-22 18:40:14 +00:00
Rafael Espindola
c4167be768 llvm-ar: align the first archive member consistently.
Before we were aligning the member after the symbol table to 4 but
other members to 8.

llvm-svn: 314010
2017-09-22 18:36:00 +00:00
Tim Shen
7c634910d0 [XRay] support conditional return on PPC.
Summary: Conditional returns were not taken into consideration at all. Implement them by turning them into jumps and normal returns. This means there is a slightly higher performance penalty for conditional returns, but this is the best we can do, and it still disturbs little of the rest.

Reviewers: dberris, echristo

Subscribers: sanjoy, nemanjai, hiraditya, kbarton, llvm-commits

Differential Revision: https://reviews.llvm.org/D38102

llvm-svn: 314005
2017-09-22 18:30:02 +00:00
Krzysztof Parzyszek
940990d757 [TableGen] Replace InfoByHwMode::getAsString with writeToStream
Also add operator<< for use with raw_ostream to InfoByHwMode and its
derived classes.

Recommitting r313989 with the fix for unresolved references: explicitly
define the operator<< in namespace llvm.

llvm-svn: 314004
2017-09-22 18:29:37 +00:00
Guozhi Wei
af71947aaf [TargetTransformInfo] Handle intrinsic call in getInstructionLatency()
Usually an intrinsic is a simple target instruction, it should have a small latency. A real function call has much larger latency. So handle the intrinsic call in function getInstructionLatency().

Differential Revision: https://reviews.llvm.org/D38104

llvm-svn: 314003
2017-09-22 18:25:53 +00:00
Rafael Espindola
76c70d6c2c llvm-ar: Don't add an unnecessary alignment in gnu mode.
This is mostly for getting stricter testing in preparation for future
changes.

llvm-svn: 314000
2017-09-22 18:16:13 +00:00
Balaram Makam
93c1975dde [Falkor] Add falkor CPU to host detection
This returns "falkor" for Falkor CPU.

llvm-svn: 313998
2017-09-22 17:46:36 +00:00
Simon Pilgrim
651f6baa77 Remove trailing whitespace. NFCI.
llvm-svn: 313996
2017-09-22 16:57:28 +00:00
Pranav Bhandarkar
36cbef5143 Check vector elements for equivalence in the HexagonVectorLoopCarriedReuse pass
If the two instructions being compared for equivalence have corresponding operands
that are integer constants, then check their values to determine equivalence.

Patch by Suyog Sarda!

llvm-svn: 313993
2017-09-22 16:43:31 +00:00
Krzysztof Parzyszek
351021b564 Revert "[TableGen] Replace InfoByHwMode::getAsString with writeToStream"
This reverts commit r313989: it breaks Windows bots.

llvm-svn: 313990
2017-09-22 16:18:35 +00:00
Krzysztof Parzyszek
d5907858f0 [TableGen] Replace InfoByHwMode::getAsString with writeToStream
Also add operator<< for use with raw_ostream to InfoByHwMode and its
derived classes.

llvm-svn: 313989
2017-09-22 16:06:35 +00:00
Daniel Neilson
91bedd1195 [SCEV] Generalize folding of trunc(x)+n*trunc(y) into folding m*trunc(x)+n*trunc(y)
Summary:
A SCEV such as:
 {%v2,+,((-1 * (trunc i64 (-1 * %v1) to i32)) + (-1 * (trunc i64 %v1 to i32)))}<%loop>

can be folded into, simply, {%v2,+,0}. However, the current code in ::getAddExpr()
will not try to apply the simplification m*trunc(x)+n*trunc(y) -> trunc(trunc(m)*x+trunc(n)*y)
because it only keys off having a non-multiplied trunc as the first term in the simplification.

This patch generalizes this code to try to do a more generic fold of these trunc
expressions.

Reviewers: sanjoy

Reviewed By: sanjoy

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D37888

llvm-svn: 313988
2017-09-22 15:47:57 +00:00
Sanjay Patel
969c9899ca [x86] remove unnecessary OS specifier from test
llvm-svn: 313986
2017-09-22 14:38:57 +00:00
Sanjay Patel
91c9495a15 [x86] auto-generate complete checks; NFC
llvm-svn: 313985
2017-09-22 14:30:52 +00:00
Sanjay Patel
fd9b40afc1 [x86] update test to use FileCheck; NFC
llvm-svn: 313984
2017-09-22 14:29:47 +00:00
Simon Pilgrim
0a1c4b0914 [TableGen] Return StringRef from ValueTypeByHwMode::getMVTName
Avoid unnecessary std::string creations during TypeSetByHwMode::writeToStream.

Found during investigations into PR28222

Differential Revision: https://reviews.llvm.org/D38174

llvm-svn: 313983
2017-09-22 13:32:26 +00:00
Alexander Ivchenko
98ceac3d19 [X86] Combining CMOVs with [ANY,SIGN,ZERO]_EXTEND for cases where CMOV has constant arguments
Combine CMOV[i16]<-[SIGN,ZERO,ANY]_EXTEND to [i32,i64] into CMOV[i32,i64].
One example of where it is useful is:

before (20 bytes)
    <foo>:
    test $0x1,%dil
    mov $0x307e,%ax
    mov $0xffff,%cx
    cmovne %ax,%cx
    movzwl %cx,%eax
    retq

after (18 bytes)
    <foo>:
    test $0x1,%dil
    mov $0x307e,%ecx
    mov $0xffff,%eax
    cmovne %ecx,%eax
    retq

Reviewers: craig.topper, aaboud, spatel, RKSimon, zvi

Reviewed By: spatel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D36711

llvm-svn: 313982
2017-09-22 13:21:39 +00:00
Artur Pilipenko
f5935363ed Rework loop predication pass
We've found a serious issue with the current implementation of loop predication.
The current implementation relies on SCEV and this turned out to be problematic.
To fix the problem we had to rework the pass substantially. We have had the
reworked implementation in our downstream tree for a while. This is the initial
patch of the series of changes to upstream the new implementation.

For now the transformation is limited to the following case:
  * The loop has a single latch with either ult or slt icmp condition.
  * The step of the IV used in the latch condition is 1.
  * The IV of the latch condition is the same as the post increment IV of the guard condition.
  * The guard condition is ult.

See the review or the LoopPredication.cpp header for the details about the
problem and the new implementation.

Reviewed By: sanjoy, mkazantsev

Differential Revision: https://reviews.llvm.org/D37569

llvm-svn: 313981
2017-09-22 13:13:57 +00:00
Nemanja Ivanovic
5ddd46e658 Remove the default clause from a fully-covering switch
to appease bots that use a compiler that warns about this
and use -Werror.

llvm-svn: 313980
2017-09-22 12:26:00 +00:00
Andre Vieira
8baad01fa3 [ARM] Fix assembly and disassembly for VMRS/VMSR
Reviewed by: t.p.northover
Differential Revision: https://reviews.llvm.org/D36306

llvm-svn: 313979
2017-09-22 12:17:42 +00:00
Nemanja Ivanovic
edbeed1075 Recommit r310809 with a fix for the spill problem
This patch re-commits the patch that was pulled out due to a
problem it caused, but with a fix for the problem. The fix
was reviewed separately by Eric Christopher and Hal Finkel.

Differential Revision: https://reviews.llvm.org/D38054

llvm-svn: 313978
2017-09-22 11:50:25 +00:00