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6 Commits

Author SHA1 Message Date
Matt Arsenault
acf5b84870 Fix typo 
llvm-svn: 210968
 2014-06-14 04:26:07 +00:00
Craig Topper
6d411cb95a [C++] Use 'nullptr'. Target edition. 
llvm-svn: 207197
 2014-04-25 05:30:21 +00:00
Tom Stellard
0971c460b5 R600: Take alignment into account when calculating the stack offset 
llvm-svn: 199826
 2014-01-22 19:24:23 +00:00
Tom Stellard
452996a15e R600: Begin private memory at the second GPR. 
This way private memory does not over-write work group information
stored in GPRs 0 and 1.

llvm-svn: 199824
 2014-01-22 19:24:19 +00:00
Tom Stellard
7c091ffbf7 R600: Fix calculation of stack offset in AMDGPUFrameLowering 
We weren't computing structure size correctly and we were relying on
the original alloca instruction to compute the offset, which isn't
always reliable.

Reviewed-by: Vincent Lejeune <vljn@ovi.com>
llvm-svn: 183568
 2013-06-07 20:52:05 +00:00
Tom Stellard
386be85491 R600: Support for indirect addressing v4 
Only implemented for R600 so far.  SI is missing implementations of a
few callbacks used by the Indirect Addressing pass and needs code to
handle frame indices.

At the moment R600 only supports array sizes of 16 dwords or less.
Register packing of vector types is currently disabled, which means that a
vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order
to correctly pack registers in all cases, we will need to implement an
analysis pass for R600 that determines the correct vector width for each
array.

v2:
  - Add support for i8 zext load from stack.
  - Coding style fixes

v3:
  - Don't reserve registers for indirect addressing when it isn't
    being used.
  - Fix bug caused by LLVM limiting the number of SubRegIndex
    declarations.

v4:
  - Fix 64-bit defines

llvm-svn: 174525
 2013-02-06 17:32:29 +00:00