1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-26 14:33:02 +02:00
Commit Graph

2064 Commits

Author SHA1 Message Date
Dan Gohman
d7301ea935 Rename MemOperand to MachineMemOperand. This was suggested by
review feedback from Chris quite a while ago. No functionality
change.

llvm-svn: 49348
2008-04-07 19:35:22 +00:00
Roman Levenstein
b40d332929 Re-commit of the r48822, where the infinite looping problem discovered
by Dan Gohman is fixed.

llvm-svn: 49330
2008-04-07 10:06:32 +00:00
Evan Cheng
497c607fae Backing out 48222 temporarily.
llvm-svn: 49124
2008-04-03 03:13:16 +00:00
Dale Johannesen
84a1314ea1 Cosmetic changes per EH patch review feedback.
llvm-svn: 49096
2008-04-02 17:04:45 +00:00
Dale Johannesen
79633a914f Recommitting EH patch; this should answer most of the
review feedback.
-enable-eh is still accepted but doesn't do anything.
EH intrinsics use Dwarf EH if the target supports that,
and are handled by LowerInvoke otherwise.
The separation of the EH table and frame move data is,
I think, logically figured out, but either one still
causes full EH info to be generated (not sure how to
split the metadata correctly).
MachineModuleInfo::needsFrameInfo is no longer used and
is removed.

llvm-svn: 49064
2008-04-02 00:25:04 +00:00
Dale Johannesen
8813206b7f Revert 49006 for the moment.
llvm-svn: 49046
2008-04-01 20:00:57 +00:00
Dale Johannesen
fa4433be71 Emit exception handling info for functions which are
not marked nounwind, or for all functions when -enable-eh
is set, provided the target supports Dwarf EH.

llvm-gcc generates nounwind in the right places; other FEs
will need to do so also.  Given such a FE, -enable-eh should
no longer be needed.

llvm-svn: 49006
2008-03-31 23:40:23 +00:00
Evan Cheng
38a755499d Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.
llvm-svn: 48995
2008-03-31 20:40:39 +00:00
Chris Lattner
49e9edd6f6 Fix "Control reaches the end of non-void function" warnings,
patch by David Chisnall.

llvm-svn: 48963
2008-03-30 18:22:13 +00:00
Roman Levenstein
55b8822511 Use a linked data structure for the uses lists of an SDNode, just like
LLVM Value/Use does and MachineRegisterInfo/MachineOperand does.
This allows constant time for all uses list maintenance operations.

The idea was suggested by Chris. Reviewed by Evan and Dan.
Patch is tested and approved by Dan.

On normal use-cases compilation speed is not affected. On very big basic
blocks there are compilation speedups in the range of 15-20% or even better. 

llvm-svn: 48822
2008-03-26 12:39:26 +00:00
Evan Cheng
6226a78cb1 Smaller function alignment when optimizing for size.
llvm-svn: 48805
2008-03-25 22:29:46 +00:00
Dan Gohman
2b96ce84aa Add explicit keywords.
llvm-svn: 48801
2008-03-25 22:06:05 +00:00
Dan Gohman
22002efa15 A quick nm audit turned up several fixed tables and objects that were
marked read-write. Use const so that they can be allocated in a
read-only segment.

llvm-svn: 48800
2008-03-25 21:45:14 +00:00
Bill Wendling
2097b72649 Use the bit size of the operand instead of the hard-coded 32 to generate the
mask.

llvm-svn: 48750
2008-03-24 23:16:37 +00:00
Duncan Sands
4153fc30c9 Introduce a new node for holding call argument
flags.  This is needed by the new legalize types
infrastructure which wants to expand the 64 bit
constants previously used to hold the flags on
32 bit machines.  There are two functional changes:
(1) in LowerArguments, if a parameter has the zext
attribute set then that is marked in the flags;
before it was being ignored; (2) PPC had some bogus
code for handling two word arguments when using the
ELF 32 ABI, which was hard to convert because of
the bogusness.  As suggested by the original author
(Nicolas Geoffray), I've disabled it for the moment.
Tested with "make check" and the Ada ACATS testsuite.

llvm-svn: 48640
2008-03-21 09:14:45 +00:00
Chris Lattner
6c4486c5c7 detabify llvm, patch by Mike Stump!
llvm-svn: 48577
2008-03-20 01:22:40 +00:00
Dan Gohman
c9dec33f3f Add support for multiple return values for the PPC target by
converting call result lowering to use the CallingConvLowering
infastructure.

llvm-svn: 48552
2008-03-19 21:39:28 +00:00
Dale Johannesen
861708b8bb Make Complex long long/double/long double work
in ppc64 mode.

llvm-svn: 48459
2008-03-17 17:11:08 +00:00
Evan Cheng
07643ce604 Unbreak JIT. Ignore TargetInstrInfo::IMPLICIT_DEF.
llvm-svn: 48447
2008-03-17 06:56:52 +00:00
Dale Johannesen
ee1e5be870 Next round of PPC32 ABI changes. Allow for gcc
behavior where a callee thinks a param will be
present in memory, even though the ABI doc says
it doesn't have to be.  Handle complex long long
and complex double (4 and 8 return regs).

llvm-svn: 48439
2008-03-17 02:13:43 +00:00
Evan Cheng
11d2c09adc Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.
llvm-svn: 48380
2008-03-15 00:03:38 +00:00
Dale Johannesen
6195ace4c0 Implement the real calling convention for ppc32 Altivec:
vectors go at the end of the memory area, after all
non-vector parameters.

llvm-svn: 48364
2008-03-14 17:41:26 +00:00
Dale Johannesen
1e54f7c2b6 Do not promote float params to double in varargs
calls here.  This was done earlier for params in
the varargs part of the params; any float params
that survive to here are in the non-varargs part,
and must not be promoted.

llvm-svn: 48310
2008-03-12 23:40:01 +00:00
Dale Johannesen
19b4c2dfaf One more bit of Altivec parameter passing.
llvm-svn: 48269
2008-03-12 00:49:20 +00:00
Dale Johannesen
460dc31418 Implement Altivec passing to varargs functions on ppc.
llvm-svn: 48264
2008-03-12 00:22:17 +00:00
Dan Gohman
8e3c88c4e9 Use PassManagerBase instead of FunctionPassManager for functions
that merely add passes. This allows them to be used with either
FunctionPassManager or PassManager, or even with a custom new
kind of pass manager.

llvm-svn: 48256
2008-03-11 22:29:46 +00:00
Dan Gohman
85bfbe2293 Generalize ExpandIntToFP to handle the case where the operand is legal
and it's the result that requires expansion. This code is a little confusing
because the TargetLoweringInfo tables for [US]INT_TO_FP use the operand type
(the integer type) rather than the result type. 

llvm-svn: 48206
2008-03-11 01:59:03 +00:00
Dale Johannesen
3278acdaaa Disable prolog code that aligns the stack when a
local object of >16 byte alignment exists.  It does not
work and getting it to work is not trivial, as explained
in the comment.  This fixes all the remaining ppc32
failures in the struct-layout-1 part of the gcc testsuite.

(gcc does not support this either, and the only way to
get such an object is with __attribute__((aligned)) or
generic vectors; it can't be done in a standard-conforming
program, or with Altivec.  So I think disabling it is OK.)

llvm-svn: 48188
2008-03-10 22:59:46 +00:00
Bill Wendling
80bc045af5 Change the "enable/disable" mechanism so that we can enable PPC register
scavenging for 32-bit and 64-bit separately.

llvm-svn: 48186
2008-03-10 22:49:16 +00:00
Evan Cheng
7d9e5a7680 Default ISD::PREFETCH to expand.
llvm-svn: 48169
2008-03-10 19:38:10 +00:00
Chris Lattner
52be2c645e fix 80 col violations.
llvm-svn: 48166
2008-03-10 18:55:53 +00:00
Nicolas Geoffray
a904844534 Stylistic modifications. No functionality changes.
llvm-svn: 48158
2008-03-10 17:46:45 +00:00
Scott Michel
bb8e8fca47 Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC's
return ValueType can depend its operands' ValueType.

This is a cosmetic change, no functionality impacted.

llvm-svn: 48145
2008-03-10 15:42:14 +00:00
Nicolas Geoffray
e3381f0f1f Add description of individual bits in CR. This fix PR1765.
llvm-svn: 48143
2008-03-10 14:12:10 +00:00
Dale Johannesen
e6b0009792 Increase ISD::ParamFlags to 64 bits. Increase the ByValSize
field to 32 bits, thus enabling correct handling of ByVal
structs bigger than 0x1ffff.  Abstract interface a bit.
Fixes gcc.c-torture/execute/pr23135.c and 
gcc.c-torture/execute/pr28982b.c in gcc testsuite (were ICE'ing
on ppc32, quietly producing wrong code on x86-32.)

llvm-svn: 48122
2008-03-10 02:17:22 +00:00
Chris Lattner
4a5abdbe3f Darwin PPC64 indirect call target goes in X12, not R12. This fixes these
two regression tests:
test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll
test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll

llvm-svn: 48120
2008-03-09 20:49:33 +00:00
Dale Johannesen
55d6e1a5aa More ppc32 byval handling (bug fixes). Things
are looking pretty good now.

llvm-svn: 48043
2008-03-08 01:41:42 +00:00
Evan Cheng
dba1dfe962 Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions.
llvm-svn: 48042
2008-03-08 00:58:38 +00:00
Dan Gohman
afeac8050d Add support for calls with i128 return values on ppc64.
llvm-svn: 48041
2008-03-08 00:19:12 +00:00
Bill Wendling
948c50e2be PPC64 passes arguments of integral type in i64 registers, not i32. Reflect this
by promoting smaller integral values (i32 at this point) to i64, then truncating
to get the wanted size.

llvm-svn: 48030
2008-03-07 20:49:02 +00:00
Dan Gohman
5bf464e1e6 Add support for lowering 128-bit shifts on ppc64.
llvm-svn: 48029
2008-03-07 20:36:53 +00:00
Dale Johannesen
3e6bacf7be Next bits of PPC byval handling. Basically functional
but there are bugs.

llvm-svn: 48028
2008-03-07 20:27:40 +00:00
Chris Lattner
08ec4919ea Add support for ppc64 shifts with 7-bit (oversized) shift amount (e.g. PPCshl).
llvm-svn: 48027
2008-03-07 20:18:24 +00:00
Chris Lattner
2f13ccc181 Replace SDT_PPCShiftOp in favor of SDTIntBinOps. This allows it to work
with 32 or 64-bit operands/results.

llvm-svn: 48026
2008-03-07 20:13:51 +00:00
Dale Johannesen
6bcc9808db Next bit of PPC ByVal handling; call-site code seems
correct now.

llvm-svn: 47978
2008-03-05 23:31:27 +00:00
Bill Wendling
37f5b4586a Removed spurious EnablePPCRS check.
llvm-svn: 47918
2008-03-04 23:27:33 +00:00
Dale Johannesen
86867d323e Move PPC lowering functions into PPCTargetLowering
class (cosmetic).  First piece of byval implementation;
this doesn't work yet.  No functional change.

llvm-svn: 47917
2008-03-04 23:17:14 +00:00
Bill Wendling
dc9de245cb Use a command-line option to turn register scavenging on/off for PPC.
llvm-svn: 47915
2008-03-04 23:13:51 +00:00
Bill Wendling
8d64999daf This is the initial check-in for adding register scavenging to PPC. (Currently,
PPC-64 doesn't work.) This also lowers the spilling of the CR registers so that
it uses a register other than the default R0 register (the scavenger scrounges
for one). A significant part of this patch fixes how kill information is
handled.

llvm-svn: 47863
2008-03-03 22:19:16 +00:00
Chris Lattner
f2a9b32eec add a note
llvm-svn: 47830
2008-03-02 19:27:34 +00:00