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17273 Commits

Author SHA1 Message Date
Evan Cheng
d7a2008a55 Revert 127368 and 127371 for now. 
llvm-svn: 127376
 2011-03-09 23:53:17 +00:00
Evan Cheng
b717770dfe Change the definition of TargetRegisterInfo::getCrossCopyRegClass to be more 
flexible.

If it returns a register class that's different from the input, then that's the
register class used for cross-register class copies.
If it returns a register class that's the same as the input, then no cross-
register class copies are needed (normal copies would do).
If it returns null, then it's not at all possible to copy registers of the
specified register class.

llvm-svn: 127368
 2011-03-09 22:47:38 +00:00
Benjamin Kramer
f1c1220d8f Fix a pasto that broke all x86_64-elf targets. 
llvm-svn: 127365
 2011-03-09 22:07:13 +00:00
Stuart Hastings
61f9a3dab2 X86 byval copies no longer always_inline. <rdar://problem/8706628> 
llvm-svn: 127359
 2011-03-09 21:10:30 +00:00
Johnny Chen
6bf5d7a170 LLVM combines the offset mode of A8.6.199 A1 & A2 into STRBT. 
The insufficient encoding information of the combined instruction confuses the decoder wrt
UQADD16.  Add extra logic to recover from that.

Fixed an assert reported by Sean Callanan

llvm-svn: 127354
 2011-03-09 20:01:14 +00:00
Bruno Cardoso Lopes
88bef593d8 Improve varags handling, with testcases. Patch by Sasa Stankovic 
llvm-svn: 127349
 2011-03-09 19:22:22 +00:00
Jan Sjödin
c7c66d9f88 Add createELFObjectTargetWriter method to TargetAsmBackend, which enables construction of non-standard ELFObjectWriters that can be used in MCJIT. 
llvm-svn: 127346
 2011-03-09 18:44:41 +00:00
NAKAMURA Takumi
fe84f8672a Target/X86: Tweak va_arg for Win64 not to miss taking va_start when number of fixed args > 4. 
llvm-svn: 127328
 2011-03-09 11:33:15 +00:00
Bill Wendling
68934338ab * Correct encoding for VSRI. 
* Add tests for VSRI and VSLI.

llvm-svn: 127297
 2011-03-09 00:33:17 +00:00
Bill Wendling
b790c462c0 Correct the encoding for VRSRA and VSRA instructions. 
llvm-svn: 127294
 2011-03-09 00:00:35 +00:00
Bill Wendling
ab9f04b6d8 * Fix VRSHR and VSHR to have the correct encoding for the immediate. 
* Update the NEON shift instruction test to expect what 'as' produces.

llvm-svn: 127293
 2011-03-08 23:48:09 +00:00
Benjamin Kramer
d5782492c8 X86: Fix the (saddo/ssub x, 1) -> incl/decl selection to check the right operand for 1. 
Found by inspection.

llvm-svn: 127247
 2011-03-08 15:20:20 +00:00
Justin Holewinski
d7426856e9 PTX: Add intrinsic support for ntid, ctaid, and nctaid registers 
llvm-svn: 127246
 2011-03-08 14:10:18 +00:00
Eric Christopher
72d7cc25f3 Turn on list-ilp scheduling by default on x86 and x86-64, fix up 
testcases accordingly. Some are currently xfailed and will be filed
as bugs to be fixed or understood.

Performance results:

roughly neutral on SPEC
some micro benchmarks in the llvm suite are up between 100 and 150%, only
a pair of regressions that are due to be investigated

john-the-ripper saw:
10% improvement in traditional DES
8% improvement in BSDI DES
59% improvement in FreeBSD MD5
67% improvement in OpenBSD Blowfish
14% improvement in LM DES

Small compile time impact.

llvm-svn: 127208
 2011-03-08 02:42:25 +00:00
Bob Wilson
f8c4d1ded9 Fix a compiler crash where a Glue value had multiple uses. Radar 9049552. 
llvm-svn: 127198
 2011-03-08 01:17:20 +00:00
Bob Wilson
94403e6221 Fix comment typos. 
llvm-svn: 127197
 2011-03-08 01:17:16 +00:00
Bill Wendling
958e854f40 Rename the narrow shift right immediate operands to "shr_imm*" operands. Also 
expand the testing of the narrowing shift right instructions.

No functionality change.

llvm-svn: 127193
 2011-03-07 23:38:41 +00:00
Cameron Zwarich
a1920d7f51 Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo. 
llvm-svn: 127175
 2011-03-07 21:56:36 +00:00
Anton Korobeynikov
8c7010e832 ARM assembler stuff is crazy: for .setfp positive values of offset corresponds to "add" instruction, not to "sub" as in .pad case 
llvm-svn: 127106
 2011-03-05 18:44:00 +00:00
Anton Korobeynikov
f15e269356 In Thumb1 mode the constant might be materialized via the load from constpool. Emit unwinding information in case when this load from constpool is used to change the stack pointer in the prologue. 
llvm-svn: 127105
 2011-03-05 18:43:55 +00:00
Anton Korobeynikov
d8873d31a8 Implement frame unwinding information emission for Thumb1. Not finished yet because there is no way given the constpool index to examine the actual entry: the reason is clones inserted by constant island pass, which are not tracked at all! The only connection is done during asmprinting time via magic label names which is really gross and needs to be eventually fixed. 
llvm-svn: 127104
 2011-03-05 18:43:50 +00:00
Anton Korobeynikov
d4828b54ec Add unwind information emission for thumb stuff 
llvm-svn: 127103
 2011-03-05 18:43:43 +00:00
Anton Korobeynikov
7ba97c2831 Handle MI flags inside Thumb2SizeReduction pass. 
llvm-svn: 127102
 2011-03-05 18:43:38 +00:00
Anton Korobeynikov
917ca94111 Preliminary support for ARM frame save directives emission via MI flags. 
This is just very first approximation how the stuff should be done
(e.g. ARM-only for now). More to follow.

llvm-svn: 127101
 2011-03-05 18:43:32 +00:00
Anton Korobeynikov
62e48532b9 Some first rudimentary support for ARM EHABI: print exception table in "text mode". 
llvm-svn: 127099
 2011-03-05 18:43:15 +00:00
Bob Wilson
1497601a7b Remove unused conditional negate operations. 
llvm-svn: 127090
 2011-03-05 16:54:31 +00:00
Che-Liang Chiou
15aba09539 ptx: add basic intrinsic support 
llvm-svn: 127084
 2011-03-05 14:17:37 +00:00
Andrew Trick
7db197d209 Increased the register pressure limit on x86_64 from 8 to 12 
regs. This is the only change in this checkin that may affects the
default scheduler. With better register tracking and heuristics, it
doesn't make sense to artificially lower the register limit so much.

Added -sched-high-latency-cycles and X86InstrInfo::isHighLatencyDef to
give the scheduler a way to account for div and sqrt on targets that
don't have an itinerary. It is currently defaults to 10 (the actual
number doesn't matter much), but only takes effect on non-default
schedulers: list-hybrid and list-ilp.

Added several heuristics that can be individually disabled for the
non-default sched=list-ilp mode. This helps us determine how much
better we can do on a given benchmark than the default
scheduler. Certain compute intensive loops run much faster in this
mode with the right set of heuristics, and it doesn't seem to have
much negative impact elsewhere. Not all of the heuristics are needed,
but we still need to experiment to decide which should be disabled by
default for sched=list-ilp.

llvm-svn: 127067
 2011-03-05 08:00:22 +00:00
Andrew Trick
5023de34d3 whitespace 
llvm-svn: 127065
 2011-03-05 06:31:54 +00:00
Bill Wendling
73b20a325f Initialize variable. 
llvm-svn: 127038
 2011-03-04 21:38:47 +00:00
Bruno Cardoso Lopes
52c64a2eb3 Improve div/rem node handling on mips. Patch by Akira Hatanaka 
llvm-svn: 127034
 2011-03-04 21:03:24 +00:00
Bruno Cardoso Lopes
e697a8bcb0 Expands register/immediate pairs when the immediate is too large to fit in 16-bit field. Patch by Akira Hatanaka 
llvm-svn: 127032
 2011-03-04 20:48:08 +00:00
Bruno Cardoso Lopes
0545e7fe48 Rewrite and simplify o32 vaarg passing, no functional changes. Patch by Sasa Stankovic 
llvm-svn: 127029
 2011-03-04 20:27:44 +00:00
Bruno Cardoso Lopes
99619e5bef Lowers block address. Currently asserts when relocation model is not PIC. Patch by Akira Hatanaka 
llvm-svn: 127027
 2011-03-04 20:01:52 +00:00
Bruno Cardoso Lopes
5347fd6512 Fix an old copy-n-paste 
llvm-svn: 127020
 2011-03-04 19:20:24 +00:00
Devang Patel
23ee9fdba3 Disable ARMGlobalMerge on darwin. The debugger is not yet able to extract individual variable's info from merged global. 
llvm-svn: 127019
 2011-03-04 19:11:05 +00:00
Bruno Cardoso Lopes
9390dc6271 Expands FCOS and FSIN nodes when type is f64. 
llvm-svn: 127017
 2011-03-04 18:54:14 +00:00
Bruno Cardoso Lopes
a49a596acf Fixes addc pattern when immediate cannot be represented with 16-bit. Patch by Akira Hatanaka 
llvm-svn: 127005
 2011-03-04 17:59:18 +00:00
Bruno Cardoso Lopes
5400401372 Remove (hopefully) all trailing whitespaces from the mips backend. Patch by Hatanaka, Akira 
llvm-svn: 127003
 2011-03-04 17:51:39 +00:00
Kalle Raiskila
6e33c92ffb Allow vector shifts (shl,lshr,ashr) on SPU. 
There was a previous implementation with patterns that would 
have matched e.g. 
	shl <v4i32> <i32>,
but this is not valid LLVM IR so they never were selected.

llvm-svn: 126998
 2011-03-04 13:19:18 +00:00
Kalle Raiskila
72cfda1a29 Allow load from constant on SPU. 
A 'load <4 x i32>* null' crashes llc before this fix.

llvm-svn: 126995
 2011-03-04 12:00:11 +00:00
Eli Friedman
be07c34368 PR9377: Handle x86 str with register operand in a way consistent with gas. 
llvm-svn: 126970
 2011-03-04 00:10:17 +00:00
Bob Wilson
c48ba54186 PR8053: Fix encoding of S bit in some ARM instructions. 
Patch by Zonr Chang!

llvm-svn: 126967
 2011-03-03 23:07:15 +00:00
Richard Osborne
88d0d840f2 Optimize fprintf -> iprintf if there are no floating point arguments 
and siprintf is available on the target.

llvm-svn: 126940
 2011-03-03 14:20:22 +00:00
Justin Holewinski
396fdaee6d PTX: Fix Emacs renaming a symbol 
llvm-svn: 126938
 2011-03-03 14:09:40 +00:00
Richard Osborne
021b589253 Optimize sprintf -> siprintf if there are no floating point arguments 
and siprintf is available on the target.

llvm-svn: 126937
 2011-03-03 14:09:28 +00:00
Justin Holewinski
86e749c620 PTX: Fix a couple of lint violations 
llvm-svn: 126936
 2011-03-03 13:34:29 +00:00
Richard Osborne
df829ddcb7 Optimize printf -> iprintf if there are no floating point arguments 
and iprintf is available on the target. Currently iprintf is only
marked as being available on the XCore.

llvm-svn: 126935
 2011-03-03 13:17:51 +00:00
Tilmann Scheller
ab6450ec63 Use X86_thiscall calling convention for Win64 as well. 
llvm-svn: 126934
 2011-03-03 07:49:07 +00:00
Bob Wilson
72ccdfe148 Add a readme entry for the redundant movw issue for pr9370. 
llvm-svn: 126930
 2011-03-03 06:39:09 +00:00