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417 Commits

Author SHA1 Message Date
Lauro Ramos Venancio
d922b8ca9b remember to emit weak reference in one more case. 
llvm-svn: 36438
 2007-04-25 14:50:40 +00:00
Evan Cheng
de9468373e Relex assertions to account for additional implicit def / use operands. 
llvm-svn: 36430
 2007-04-25 07:12:14 +00:00
Dale Johannesen
5f27e8bcc4 Make Thumb funcs containing islands 4-byte aligned. Fix bugs maintaining 
BBOffsets and BBSizes when adjusting conditional branches.

llvm-svn: 36372
 2007-04-23 20:09:04 +00:00
Dale Johannesen
f7d3443fa7 add Align field, and use when generating function alignment 
llvm-svn: 36371
 2007-04-23 20:07:25 +00:00
Dale Johannesen
9dce0dffd1 add isThumb (unused as yet) 
llvm-svn: 36370
 2007-04-23 20:04:35 +00:00
Lauro Ramos Venancio
f8b49e5ee0 Implement PIC for arm-linux. 
llvm-svn: 36324
 2007-04-22 00:04:12 +00:00
Evan Cheng
20c6a03b60 Specify S registers as D registers' sub-registers. 
llvm-svn: 36280
 2007-04-20 21:20:10 +00:00
Chris Lattner
f7ac47b4e2 add a crazy idea 
llvm-svn: 36273
 2007-04-20 20:18:43 +00:00
Lauro Ramos Venancio
5e0a3ef555 Fix a bug in getFrameRegister. 
Reported by Raul Herbster.

llvm-svn: 36262
 2007-04-19 14:09:38 +00:00
Chris Lattner
87296c2580 dag combiner just got better at pruning bits. This fixes CodeGen/ARM/rev.ll 
llvm-svn: 36222
 2007-04-17 22:39:58 +00:00
Chris Lattner
af5c203dbd add a note 
llvm-svn: 36203
 2007-04-17 18:03:00 +00:00
Anton Korobeynikov
f3e62a428a Removed tabs everywhere except autogenerated & external files. Add make 
target for tabs checking.

llvm-svn: 36146
 2007-04-16 18:10:23 +00:00
Chris Lattner
e7cab7b7a4 arm has r+r*s and r+i addr modes, but no r+i+r*s addr modes. 
llvm-svn: 35962
 2007-04-13 06:50:55 +00:00
Chris Lattner
e9a9a3f172 Fix incorrect fall-throughs in addr mode code. This fixes CodeGen/ARM/arm-negative-stride.ll 
llvm-svn: 35909
 2007-04-11 16:17:12 +00:00
Chris Lattner
3bbd376057 restore support for negative strides 
llvm-svn: 35859
 2007-04-10 03:48:29 +00:00
Chris Lattner
98199016ae remove dead target hooks 
llvm-svn: 35846
 2007-04-09 23:33:39 +00:00
Chris Lattner
ae6e2c0ee5 remove some dead target hooks, subsumed by isLegalAddressingMode 
llvm-svn: 35840
 2007-04-09 22:27:04 +00:00
Evan Cheng
44488cb676 Implement inline asm modifier P. 
llvm-svn: 35640
 2007-04-04 00:13:29 +00:00
Evan Cheng
d5956e4409 Typo. 
llvm-svn: 35639
 2007-04-04 00:06:07 +00:00
Evan Cheng
2cd9df6983 Remove unused constant pool entries. 
llvm-svn: 35635
 2007-04-03 23:39:48 +00:00
Evan Cheng
db15aa24f9 Fixed a bug that causes codegen of noop like add r0, r0, #0. 
llvm-svn: 35627
 2007-04-03 21:31:21 +00:00
Evan Cheng
16696f0ad8 Inverted logic. 
llvm-svn: 35619
 2007-04-03 06:44:25 +00:00
Chris Lattner
4d702a890c Arm supports negative strides as well, add them. This lets us compile: 
CodeGen/ARM/arm-negative-stride.ll to:

LBB1_2: @bb
        str r1, [r3, -r0, lsl #2]
        add r0, r0, #1
        cmp r0, r2
        bne LBB1_2      @bb

llvm-svn: 35609
 2007-04-03 00:13:57 +00:00
Dale Johannesen
e1c3dc7c78 fix off by 1 error in displacement computation 
llvm-svn: 35602
 2007-04-02 20:31:06 +00:00
Chris Lattner
726d461daf fix the CodeGen/ARM/2007-03-13-InstrSched.ll regression: allow IV's with scales 
to be folded into non-store instructions.

llvm-svn: 35601
 2007-04-02 18:51:18 +00:00
Chris Lattner
ff9caac83e add support for the 'w' inline asm register class. 
llvm-svn: 35598
 2007-04-02 17:24:08 +00:00
Lauro Ramos Venancio
7e21418680 - Divides the comparisons in two types: comparisons that only use N and Z 
flags (ARMISD::CMPNZ) and comparisons that use all flags (ARMISD::CMP).
- Defines the instructions: TST, TEQ (ARM) and TST (Thumb).

llvm-svn: 35573
 2007-04-02 01:30:03 +00:00
Evan Cheng
949a34fbad Add i16 address mode. 
llvm-svn: 35551
 2007-04-01 08:06:46 +00:00
Chris Lattner
c0405a348d implement the new addressing mode description hook. 
llvm-svn: 35521
 2007-03-30 23:15:24 +00:00
Evan Cheng
526a67c09b New entry. 
llvm-svn: 35480
 2007-03-29 21:40:13 +00:00
Evan Cheng
3a6b488265 Can't re-materialize mov r, imm in thumb since mov would clobber the condition code. 
llvm-svn: 35479
 2007-03-29 21:38:31 +00:00
Evan Cheng
bde0409264 Add support for hidden visibility to darwin/arm. 
llvm-svn: 35448
 2007-03-29 07:49:34 +00:00
Evan Cheng
a55449c051 Remove isLegalAddressImmediate. 
llvm-svn: 35406
 2007-03-28 01:53:55 +00:00
Lauro Ramos Venancio
8b2e32de5a bugfix: sometimes the spiller puts a load between the "mov lr, pc" and "bx" of a CALL_NOLINK. 
llvm-svn: 35381
 2007-03-27 16:19:21 +00:00
Evan Cheng
968135bd3f findRegisterUseOperand() changed. 
llvm-svn: 35366
 2007-03-26 22:41:48 +00:00
Chris Lattner
b19069959d switch TargetLowering::getConstraintType to take the entire constraint, 
not just the first letter.  No functionality change.

llvm-svn: 35322
 2007-03-25 02:14:49 +00:00
Dale Johannesen
44c0a5d545 repair x86 performance, dejagnu problems from previous change 
llvm-svn: 35245
 2007-03-21 21:51:52 +00:00
Evan Cheng
fb9c4c2edc Updated. 
llvm-svn: 35229
 2007-03-20 22:32:39 +00:00
Dale Johannesen
3e422e3b49 do not share old induction variables when this would result in invalid 
instructions (that would have to be split later)

llvm-svn: 35227
 2007-03-20 21:54:54 +00:00
Lauro Ramos Venancio
11d7d3fcaf bugfix: When the source register of CALL_NOLINK was LR, the following code was emitted: 
mov lr, pc
    bx lr
So, the function was not called.

llvm-svn: 35218
 2007-03-20 17:57:23 +00:00
Evan Cheng
4fec9d7228 Make two piece constant generation as a single instruction. It's re-materialized as a load from constantpool. 
llvm-svn: 35207
 2007-03-20 08:11:30 +00:00
Evan Cheng
11976abd1e New entry. 
llvm-svn: 35206
 2007-03-20 08:10:17 +00:00
Evan Cheng
41f4f032ee Added MRegisterInfo hook to re-materialize an instruction. 
llvm-svn: 35205
 2007-03-20 08:09:38 +00:00
Chris Lattner
1ed603c0d9 fix indentation 
llvm-svn: 35202
 2007-03-20 02:25:53 +00:00
Dale Johannesen
c526b970ce fix obvious comment bug 
llvm-svn: 35196
 2007-03-20 00:30:56 +00:00
Evan Cheng
8d374caead Fix naming inconsistencies. 
llvm-svn: 35163
 2007-03-19 07:48:02 +00:00
Evan Cheng
7cbf4c4582 Special LDR instructions to load from non-pc-relative constantpools. These are 
rematerializable. Only used for constant generation for now.

llvm-svn: 35162
 2007-03-19 07:20:03 +00:00
Evan Cheng
389cf8e719 Constant generation instructions are re-materializable. 
llvm-svn: 35161
 2007-03-19 07:09:02 +00:00
Lauro Ramos Venancio
f756184c5e Only ARMv6 has BSWAP. 
Fix MultiSource/Applications/aha test.

llvm-svn: 35128
 2007-03-16 22:54:16 +00:00
Evan Cheng
4858c6f781 Added isLegalAddressExpression(). Only allows X +/- C for now. 
llvm-svn: 35122
 2007-03-16 08:43:56 +00:00