1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-26 04:32:44 +01:00
Commit Graph

33 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
32f1783ca1 Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.
These functions not longer assert when passed 0, but simply return false instead.

No functional change intended.

llvm-svn: 123155
2011-01-10 02:58:51 +00:00
Evan Cheng
aa16fd02ad Do not model all INLINEASM instructions as having unmodelled side effects.
Instead encode llvm IR level property "HasSideEffects" in an operand (shared
with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check
the operand when the instruction is an INLINEASM.

This allows memory instructions to be moved around INLINEASM instructions.

llvm-svn: 123044
2011-01-07 23:50:32 +00:00
Owen Anderson
46990c17f7 Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which
must be called in the pass's constructor.  This function uses static dependency declarations to recursively initialize
the pass's dependencies.

Clients that only create passes through the createFooPass() APIs will require no changes.  Clients that want to use the
CommandLine options for passes will need to manually call the appropriate initialization functions in PassInitialization.h
before parsing commandline arguments.

I have tested this with all standard configurations of clang and llvm-gcc on Darwin.  It is possible that there are problems
with the static dependencies that will only be visible with non-standard options.  If you encounter any crash in pass
registration/creation, please send the testcase to me directly.

llvm-svn: 116820
2010-10-19 17:21:58 +00:00
Owen Anderson
69cbf2e8b7 Now with fewer extraneous semicolons!
llvm-svn: 115996
2010-10-07 22:25:06 +00:00
Jakob Stoklund Olesen
9fe6b84fb2 Track liveness of unallocatable, unreserved registers in machine DCE.
Reserved registers are unpredictable, and are treated as always live by machine
DCE.

Allocatable registers are never reserved, and can be used for virtual registers.

Unreserved, unallocatable registers can not be used for virtual registers, but
otherwise behave like a normal allocatable register. Most targets only have
the flag register in this set.

llvm-svn: 112649
2010-08-31 21:51:05 +00:00
Owen Anderson
f2fea95f2f Reapply r110396, with fixes to appease the Linux buildbot gods.
llvm-svn: 110460
2010-08-06 18:33:48 +00:00
Owen Anderson
aadd8a89ca Revert r110396 to fix buildbots.
llvm-svn: 110410
2010-08-06 00:23:35 +00:00
Owen Anderson
b9762c07cb Don't use PassInfo* as a type identifier for passes. Instead, use the address of the static
ID member as the sole unique type identifier.  Clean up APIs related to this change.

llvm-svn: 110396
2010-08-05 23:42:04 +00:00
Owen Anderson
f8addbb0a1 Fix batch of converting RegisterPass<> to INTIALIZE_PASS().
llvm-svn: 109045
2010-07-21 22:09:45 +00:00
Evan Cheng
a93cb01841 Swap parameters of isSafeToMove and isSafeToReMat for consistency.
llvm-svn: 97578
2010-03-02 19:03:01 +00:00
Dale Johannesen
c7b5b1dcfa Rewrite handling of DBG_VALUE; previous algorithm
didn't handle
X =
Y<dead> = use X
DBG_VALUE(X)
I was hoping to avoid this approach as it's slower,
but I don't think it can be done.

llvm-svn: 95996
2010-02-12 18:40:17 +00:00
Dale Johannesen
810ebb35c9 Allow for more than one DBG_VALUE targeting the
same dead instruction.

llvm-svn: 95890
2010-02-11 18:23:23 +00:00
Bob Wilson
82d5534acc Delete dead PHI machine instructions. These can be created due to type
legalization even when the IR-level optimizer has removed dead phis, such
as when the high half of an i64 value is unused on a 32-bit target.
I had to adjust a few test cases that had dead phis.
This is a partial fix for Radar 7627077.

llvm-svn: 95816
2010-02-10 22:58:57 +00:00
Dale Johannesen
da728faa59 more comment updates
llvm-svn: 95736
2010-02-10 00:44:23 +00:00
Chris Lattner
7acf9be6c4 move target-independent opcodes out of TargetInstrInfo
into TargetOpcodes.h.  #include the new TargetOpcodes.h
into MachineInstr.  Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the 
codebase.

llvm-svn: 95687
2010-02-09 19:54:29 +00:00
Evan Cheng
5541068ad3 Run codegen dce pass for all targets at all optimization levels. Previously it's
only run for x86 with fastisel. I've found it being very effective in
eliminating some obvious dead code as result of formal parameter lowering
especially when tail call optimization eliminated the need for some of the loads
from fixed frame objects. It also shrinks a number of the tests. A couple of
tests no longer make sense and are now eliminated.

llvm-svn: 95493
2010-02-06 09:07:11 +00:00
Dale Johannesen
74ab14a99f If the only use of something is a DEBUG_VALUE, don't
let that stop it from being deleted, and change the
DEBUG_VALUE value to undef.

llvm-svn: 94694
2010-01-27 22:12:36 +00:00
David Greene
11dfd04083 Change errs() to dbgs().
llvm-svn: 92496
2010-01-04 19:10:20 +00:00
Nick Lewycky
2b8400628d Remove includes of Support/Compiler.h that are no longer needed after the
VISIBILITY_HIDDEN removal.

llvm-svn: 85043
2009-10-25 06:57:41 +00:00
Nick Lewycky
711c726c97 Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.
Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.

llvm-svn: 85042
2009-10-25 06:33:48 +00:00
Dan Gohman
5bfc2416fe Factor out LiveIntervalAnalysis' code to determine whether an instruction
is trivially rematerializable and integrate it into
TargetInstrInfo::isTriviallyReMaterializable. This way, all places that
need to know whether an instruction is rematerializable will get the
same answer.

This enables the useful parts of the aggressive-remat option by
default -- using AliasAnalysis to determine whether a memory location
is invariant, and removes the questionable parts -- rematting operations
with virtual register inputs that may not be live everywhere.

llvm-svn: 83687
2009-10-09 23:27:56 +00:00
Bill Wendling
d197f257a7 Convert DOUT to DEBUG(errs()...).
llvm-svn: 79748
2009-08-22 20:04:03 +00:00
Dan Gohman
abb3e2d240 Add const qualifiers.
llvm-svn: 78663
2009-08-11 15:13:43 +00:00
Dan Gohman
3526f97d13 Rename AliasSet to SubRegs, to reflect changes in the surrounding code.
llvm-svn: 57618
2008-10-16 01:06:18 +00:00
Dan Gohman
8075c32a55 Fix a subtle bug in DeadMachineInstructionElim's liveness
computation. A def of a register doesn't necessarily kill
live super-registers.

llvm-svn: 57614
2008-10-16 00:11:23 +00:00
Dan Gohman
30c5ce1b7d Switch the MachineOperand accessors back to the short names like
isReg, etc., from isRegister, etc.

llvm-svn: 57006
2008-10-03 15:45:36 +00:00
Dan Gohman
32c4066d62 Add debug output to this pass.
llvm-svn: 56602
2008-09-25 01:06:50 +00:00
Dan Gohman
a7a04d8ae6 Refactor the logic for testing if an instruction is dead into a
separate method.

llvm-svn: 56531
2008-09-24 00:27:38 +00:00
Dan Gohman
49becd6c31 Set SetStore to false, to allow this pass to delete
dead loads.

llvm-svn: 56529
2008-09-24 00:07:08 +00:00
Dan Gohman
583938816c Now that DeadMachineInstructionElim is basically working
correctly, it's not necessary to explicitly remove registers
from their use-def lists.

llvm-svn: 56509
2008-09-23 22:04:18 +00:00
Dan Gohman
3242b7c44c Track local physical register liveness. This is not the most
efficient implementation possible, but it's pretty simple and
good enough for the time being.

llvm-svn: 56504
2008-09-23 21:40:44 +00:00
Dan Gohman
9dc56fbe40 Don't consider instructions with implicit physical register
defs to be necessarily live.

llvm-svn: 56310
2008-09-18 18:22:32 +00:00
Dan Gohman
d0c6cb65e8 Add a new MachineInstr-level DCE pass. It is very simple, and is intended to
be used with fast-isel.

llvm-svn: 56268
2008-09-17 00:43:24 +00:00