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287 Commits

Author SHA1 Message Date
Evan Cheng
ba77bacf48 Model VST*_UPD and VST*oddUPD pair with REG_SEQUENCE. 
llvm-svn: 103833
 2010-05-14 22:54:52 +00:00
Evan Cheng
ab9e0f7315 Model VLD*_UPD and VLD*odd_UPD pair with REG_SEQUENCE. 
llvm-svn: 103790
 2010-05-14 18:54:59 +00:00
Evan Cheng
d1f60c198d Fix comments. 
llvm-svn: 103749
 2010-05-14 00:21:45 +00:00
Evan Cheng
5311f25b0b Model some vst3 and vst4 with reg_sequence. 
llvm-svn: 103453
 2010-05-11 01:19:40 +00:00
Evan Cheng
91747dc5dc Model some vld3 instructions with REG_SEQUENCE. 
llvm-svn: 103437
 2010-05-10 21:26:24 +00:00
Evan Cheng
7f0d8f1ab0 Model vld2 / vst2 with reg_sequence. 
llvm-svn: 103411
 2010-05-10 17:34:18 +00:00
Bob Wilson
e5f295c76d Add a missing break statement to fix unintentional fall-through 
(replacing the previous patch for the same issue).

llvm-svn: 103183
 2010-05-06 16:05:26 +00:00
Jim Grosbach
bffae8af60 Fix unintentional fallthrough. Patch by Edmund Grimley-Evans <Edmund.Grimley-Evans@arm.com> 
llvm-svn: 103181
 2010-05-06 15:32:49 +00:00
Evan Cheng
6a76e7d9ae Model CONCAT_VECTORS of two 64-bit values as a REG_SEQUENCE. 
llvm-svn: 103104
 2010-05-05 18:28:36 +00:00
Evan Cheng
1440201528 With -neon-reg-sequence, models forming a Q register from a pair of consecutive D registers as a REG_SEQUENCE. 
llvm-svn: 103047
 2010-05-04 20:39:49 +00:00
Jim Grosbach
b9dccb6103 Update ARM DAGtoDAG for matching UBFX instruction for unsigned bitfield 
extraction. This fixes PR5998.

llvm-svn: 102144
 2010-04-22 23:24:18 +00:00
Dan Gohman
a0f855157e Use const qualifiers with TargetLowering. This eliminates several 
const_casts, and it reinforces the design of the Target classes being
immutable.

SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.

And PIC16's AsmPrinter no longer uses TargetLowering.

llvm-svn: 101635
 2010-04-17 15:26:15 +00:00
Evan Cheng
428f7f39a8 Use getAL() rather than a major constant. 
llvm-svn: 101446
 2010-04-16 05:46:06 +00:00
Evan Cheng
c843326d60 Use default lowering of DYNAMIC_STACKALLOC. As far as I can tell, ARM isle is doing the right thing and codegen looks correct for both Thumb and Thumb2. 
llvm-svn: 101410
 2010-04-15 22:20:34 +00:00
Evan Cheng
2f6d7ecd1b ARM SelectDYN_ALLOC should emit a copy from SP rather than referencing SP directly. In cases where there are two dyn_alloc in the same BB it would have caused the old SP value to be reused and badness ensues. rdar://7493908 
llvm is generating poor code for dynamic alloca, I'll fix that later.

llvm-svn: 101383
 2010-04-15 18:42:28 +00:00
Bob Wilson
195c570fd3 Fix VLDMQ and VSTMQ instructions to use the correct encoding and address modes. 
These instructions are only needed for codegen, so I've removed all the
explicit encoding bits for now; they should be set in the same way as the for
VLDMD and VSTMD whenever we add encodings for VFP.  The use of addrmode5
requires that the instructions be custom-selected so that the number of
registers can be set in the AM5Opc value.

llvm-svn: 99309
 2010-03-23 18:54:46 +00:00
Bob Wilson
58c4740582 Change VST1 instructions for loading Q register values to operate on pairs 
of D registers.  Add a separate VST1q instruction with a Q register
source operand for use by storeRegToStackSlot.

llvm-svn: 99265
 2010-03-23 06:20:33 +00:00
Bob Wilson
2764399dd8 Change VLD1 instructions for loading Q register values to operate on pairs 
of D registers.  Add a separate VLD1q instruction with a Q register
destination operand for use by loadRegFromStackSlot.

llvm-svn: 99261
 2010-03-23 05:25:43 +00:00
Bob Wilson
f23a45e151 Rename some VLD1/VST1 instructions to match the implementation, i.e., the 
corresponding NEON instructions, instead of operation they are currently
used for.

llvm-svn: 99189
 2010-03-22 18:13:18 +00:00
Bob Wilson
73d7323c91 Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6") 
with changes to add a separate optional register update argument.  Change all
the NEON instructions with address register writeback to use it.

llvm-svn: 99095
 2010-03-20 22:13:40 +00:00
Bob Wilson
a98f30a3a2 Rename some instructions for consistency and sanity: use "_UPD" suffix for 
load/stores with address register writeback, and use "odd" suffix to distinguish
instructions to access odd numbered registers (instead of "a" and "b").
No functional changes.

llvm-svn: 99066
 2010-03-20 18:35:24 +00:00
Bob Wilson
3778e7f389 Revert 98683. It is breaking something in the disassembler. 
llvm-svn: 98692
 2010-03-16 23:01:13 +00:00
Bob Wilson
79f10e6233 Remove redundant writeback flag from ARM address mode 6. Also remove the 
optional register update argument, which is currently unused -- when we add
support for that, it can just be a separate operand.

llvm-svn: 98683
 2010-03-16 21:44:40 +00:00
Chris Lattner
1707a88a2c Sink InstructionSelect() out of each target into SDISel, and rename it 
DoInstructionSelection.  Inline "SelectRoot" into it from DAGISelHeader.
Sink some other stuff out of DAGISelHeader into SDISel.

Eliminate the various 'Indent' stuff from various targets, which dates
to when isel was recursive.

 17 files changed, 114 insertions(+), 430 deletions(-)

llvm-svn: 97555
 2010-03-02 06:34:30 +00:00
Evan Cheng
b5fe25544c Split SelectionDAGISel::IsLegalAndProfitableToFold to 
IsLegalToFold and IsProfitableToFold. The generic version of the later simply checks whether the folding candidate has a single use.

This allows the target isel routines more flexibility in deciding whether folding makes sense. The specific case we are interested in is folding constant pool loads with multiple uses.

llvm-svn: 96255
 2010-02-15 19:41:07 +00:00
Chris Lattner
7acf9be6c4 move target-independent opcodes out of TargetInstrInfo 
into TargetOpcodes.h.  #include the new TargetOpcodes.h
into MachineInstr.  Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the 
codebase.

llvm-svn: 95687
 2010-02-09 19:54:29 +00:00
Evan Cheng
f1a3f81a1d Fix r93758. Use isel patterns instead of c++ selection code to select rbit and make sure we pick different instructions for ARM vs. Thumb2. 
llvm-svn: 93829
 2010-01-19 00:44:15 +00:00
Jim Grosbach
70af2216fd Patch by David Conrad: 
"On ARMv6T2 this turns cttz into rbit, clz instead of the 4 instruction
 sequence it is now."

llvm-svn: 93758
 2010-01-18 19:58:49 +00:00
Bob Wilson
b4c16ab0b3 Fix an off-by-one error that caused the chain operand to be dropped from Neon 
vector load-lane and store-lane instructions.

llvm-svn: 93673
 2010-01-17 05:58:23 +00:00
Dan Gohman
9bcfdf98f1 Change SelectCode's argument from SDValue to SDNode *, to make it more 
clear what information these functions are actually using.

This is also a micro-optimization, as passing a SDNode * around is
simpler than passing a { SDNode *, int } by value or reference.

llvm-svn: 92564
 2010-01-05 01:24:18 +00:00
Anton Korobeynikov
0f885eb7fd Materialize global addresses via movt/movw pair, this is always better 
than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.

This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).

llvm-svn: 89720
 2009-11-24 00:44:37 +00:00
Evan Cheng
a7496ef9a6 Add predicate operand to NEON instructions. Fix lots (but not all) 80 col violations in ARMInstrNEON.td. 
llvm-svn: 89542
 2009-11-21 06:21:52 +00:00
Evan Cheng
405012b096 Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all. 
llvm-svn: 89423
 2009-11-20 00:54:03 +00:00
Evan Cheng
af22254deb Refactor cmov selection code out to a separate function. No functionality change. 
llvm-svn: 89396
 2009-11-19 21:45:22 +00:00
Evan Cheng
9730c9113e 80 col violation. 
llvm-svn: 89337
 2009-11-19 08:16:50 +00:00
Jim Grosbach
ea6c9c17f5 Use Unified Assembly Syntax for the ARM backend. 
llvm-svn: 86494
 2009-11-09 00:11:35 +00:00
Jim Grosbach
73c1e315e1 Support alignment specifier for NEON vld/vst instructions 
llvm-svn: 86404
 2009-11-07 21:25:39 +00:00
Dan Gohman
eec0f1c506 Remove uninteresting and confusing debug output. 
llvm-svn: 86149
 2009-11-05 18:47:09 +00:00
Bob Wilson
ac53e0c640 Prune unnecessary include. 
llvm-svn: 85805
 2009-11-02 16:58:31 +00:00
Johnny Chen
37851c95e8 Test commit. Added '.' to the comment line. 
llvm-svn: 85255
 2009-10-27 17:25:15 +00:00
Evan Cheng
8fdd1661fa Don't generate sbfx / ubfx with negative lsb field. Patch by David Conrad. 
llvm-svn: 84813
 2009-10-22 00:40:00 +00:00
Evan Cheng
275a09e55d Match more patterns to movt. 
llvm-svn: 84751
 2009-10-21 08:15:52 +00:00
Bob Wilson
1554029c7c Remove unused variables to fix build warning. 
llvm-svn: 84144
 2009-10-14 21:40:45 +00:00
Bob Wilson
320891060f Refactor code to select NEON VST intrinsics. 
llvm-svn: 84122
 2009-10-14 18:32:29 +00:00
Bob Wilson
2b19bbea06 Refactor code to select NEON VLD intrinsics. 
llvm-svn: 84117
 2009-10-14 17:28:52 +00:00
Bob Wilson
5dbe1c0143 More refactoring. NEON vst lane intrinsics can share almost all the code for 
vld lane intrinsics.

llvm-svn: 84110
 2009-10-14 16:46:45 +00:00
Bob Wilson
7623a1ce5c Refactor code for selecting NEON load lane intrinsics. 
llvm-svn: 84109
 2009-10-14 16:19:03 +00:00
Bob Wilson
a98883deaa More Neon clean-up: avoid the need for custom-lowering vld/st-lane intrinsics 
by creating TargetConstants during instruction selection instead of during
legalization.

llvm-svn: 84042
 2009-10-13 22:29:24 +00:00
Bob Wilson
d66a3fd73b Revise ARM inline assembly memory operands to require the memory address to 
be in a register.  The previous use of ARM address mode 2 was completely
arbitrary and inappropriate for Thumb.  Radar 7137468.

llvm-svn: 84022
 2009-10-13 20:50:28 +00:00
Sandeep Patel
af459ed32d Fix method name in comment, per Bob Wilson. 
llvm-svn: 84017
 2009-10-13 20:25:58 +00:00