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Commit Graph

62073 Commits

Author SHA1 Message Date
Ulrich Weigand
da66ee086f [PowerPC] Add rldcr/rldic instructions
This adds pattern for the rldcr and rldic instructions (the last instruction
from the rotate/shift family that were missing).  They are currently used
only by the asm parser.

llvm-svn: 184833
2013-06-25 13:17:10 +00:00
Ulrich Weigand
d51b3cd01b [PowerPC] Add extended subtract mnemonics
This adds support for the extended subtract mnemonics to the asm parser:
   subi
   subis
   subic
   subic.
   sub
   sub.
   subc
   subc.
 

llvm-svn: 184832
2013-06-25 13:16:48 +00:00
Justin Holewinski
f085b28335 [NVPTX] Default pointer type doesn't make sense for getParamSymbol()
llvm-svn: 184831
2013-06-25 12:22:21 +00:00
Nadav Rotem
8fcb707c24 Fix a typo in the code that collected the costs recursively.
llvm-svn: 184827
2013-06-25 05:30:56 +00:00
Rafael Espindola
35fe018057 keep only the StringRef version of getFileOrSTDIN.
llvm-svn: 184826
2013-06-25 05:28:34 +00:00
Rafael Espindola
525437f64a Don't assume ResultPath is null terminated.
llvm-svn: 184824
2013-06-25 04:23:46 +00:00
Andrew Trick
18751012bb Revert "Temporarily enable MI-Sched on X86."
This reverts commit 98a9b72e8c56dc13a2617de84503a3d78352789c.

llvm-svn: 184823
2013-06-25 02:48:58 +00:00
Tom Stellard
fa154aaa39 R600/SI: Report unaligned memory accesses as legal for > 32-bit types
In reality, some unaligned memory accesses are legal for 32-bit types and
smaller too, but it all depends on the address space.  Allowing
unaligned loads/stores for > 32-bit types is mainly to prevent the
legalizer from splitting one load into multiple loads of smaller types.

https://bugs.freedesktop.org/show_bug.cgi?id=65873

llvm-svn: 184822
2013-06-25 02:39:35 +00:00
Tom Stellard
ddc78167d3 R600: Add support for i32 loads from the constant address space on Cayman
Tested-By: Aaron Watry <awatry@gmail.com>
llvm-svn: 184821
2013-06-25 02:39:30 +00:00
Tom Stellard
b4ab710b43 R600/SI: Add support for v4i32 and v4f32 kernel args
Tested-By: Aaron Watry <awatry@gmail.com>
llvm-svn: 184820
2013-06-25 02:39:25 +00:00
Tom Stellard
0300b2cb3a R600: Fix typo in R600Schedule.td
This should only make a difference in programs that use a lot of the
vector ALU instructions like BFI_INT and BIT_ALIGN.  There is a slight
improvement in the phatk bitcoin mining kernel with this patch on
Evergreen (vector size == 1):

Before:
1173 Instruction Groups / 9520 dwords

After:
1167 Instruction Groups / 9510 dwords

Reviewed-by: Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 184819
2013-06-25 02:39:20 +00:00
NAKAMURA Takumi
c0b121df0b PPCAsmParser.cpp: Quote "@l/@ha" in comments. [-Wdocumentation]
llvm-svn: 184809
2013-06-25 01:14:20 +00:00
Rafael Espindola
df18681407 Cleanup in unique_file when we only want the name.
This is really ugly, but it is no worse than what we have in clang right now and
it is better to get it working first and clean/optimize it afterwards.

Will be tested from clang in the next patch.

llvm-svn: 184802
2013-06-25 00:49:40 +00:00
Eric Christopher
85478a853a 80-column and tab character fixes.
llvm-svn: 184792
2013-06-24 23:20:02 +00:00
Eric Christopher
6abbfb6bb7 Formatting.
llvm-svn: 184788
2013-06-24 21:34:55 +00:00
Adrian Prantl
3768276ade typo.
llvm-svn: 184783
2013-06-24 21:19:43 +00:00
Eric Christopher
50e46e8378 Use const references instead of pointers to references that are
never modified. No functional change.

llvm-svn: 184781
2013-06-24 21:07:27 +00:00
Ulrich Weigand
655ef3283d [PowerPC] Support some miscellaneous mnemonics in the asm parser
This adds support for the following extended mnemonics:
  xnop
  mr.
  not
  not.
  la

llvm-svn: 184767
2013-06-24 18:08:03 +00:00
David Blaikie
2bf3b1e948 DebugInfo: DIBuilder changes to match DIEnumerator changes in r184694
Representing enumerators by int64 instead of uint64 for now. At some
point we need to address the underlying issue of representation
depending on the specific enumeration.

llvm-svn: 184761
2013-06-24 17:34:33 +00:00
Benjamin Kramer
bc7599b681 PPC: Remove default case from fully covered switch.
llvm-svn: 184758
2013-06-24 17:03:25 +00:00
Aaron Watry
d3d63bb8fd R600: Fix spelling error in comment
our -> or

llvm-svn: 184756
2013-06-24 16:57:57 +00:00
Ulrich Weigand
719e95004a [PowerPC] Add predicted forms of branches
This adds support for the predicted forms of branches (+/-).
There are three cases to consider:
- Branches using a PPC::Predicate code
  For these, I've added new PPC::Predicate codes corresponding
  to the BO values for predicted branch forms, and updated insn
  printing to print them correctly.  I've also added new aliases
  for the asm parser matching the new forms.
- bt/bf
  I've added new aliases matching to gBC etc.
- bd(n)z variants
  I've added new instruction patterns for the predicted forms.

In all cases, the new patterns are used for the asm parser only.
(The new infrastructure ought to be sufficient to allow use by
the compiler too at some point.)

llvm-svn: 184754
2013-06-24 16:52:04 +00:00
Nadav Rotem
eff545235c Rename the variable to fix a warning. Thanks Andy Gibbs.
llvm-svn: 184749
2013-06-24 15:59:47 +00:00
NAKAMURA Takumi
c94525d76e NVPTXTargetObjectFile.h: Initialize some pointers as NULL in the constructor of NVPTXTargetObjectFile. ~NVPTXTargetObjectFile() tries to delete them.
It caused crash on some hosts since r184595.

llvm-svn: 184728
2013-06-24 13:19:41 +00:00
Ulrich Weigand
5349a508ea [PowerPC] Add t/f branch mnemonics to asm parser
This adds the bt/bf/bd(n)zt/bd(n)zf mnemonics as aliases for the
asm parser, resolving to the generic conditional patterns.

llvm-svn: 184725
2013-06-24 12:49:20 +00:00
Arnold Schwaighofer
0a98597e80 Reapply 184685 after the SetVector iteration order fix.
This should hopefully have fixed the stage2/stage3 miscompare on the dragonegg
testers.

"LoopVectorize: Use the dependence test utility class

We now no longer need alias analysis - the cases that alias analysis would
handle are now handled as accesses with a large dependence distance.

We can now vectorize loops with simple constant dependence distances.

  for (i = 8; i < 256; ++i) {
    a[i] = a[i+4] * a[i+8];
  }

  for (i = 8; i < 256; ++i) {
    a[i] = a[i-4] * a[i-8];
  }

We would be able to vectorize about 200 more loops (in many cases the cost model
instructs us no to) in the test suite now. Results on x86-64 are a wash.

I have seen one degradation in ammp. Interestingly, the function in which we
now vectorize a loop is never executed so we probably see some instruction
cache effects. There is a 2% improvement in h264ref. There is one or the other
TSCV loop kernel that speeds up.

radar://13681598"

llvm-svn: 184724
2013-06-24 12:09:15 +00:00
Arnold Schwaighofer
75b76bf92f LoopVectorize: Use SetVector for the access set
We are creating the runtime checks using this set so we need a deterministic
iteration order.

llvm-svn: 184723
2013-06-24 12:09:12 +00:00
Ulrich Weigand
5f83058705 [PowerPC] Support generic conditional branches in asm parser
This adds instruction patterns to cover the generic forms of
the conditional branch instructions.  This allows the assembler
to support the generic mnemonics.

The compiler will still generate the various specific forms
of the instruction that were already supported.

llvm-svn: 184722
2013-06-24 11:55:21 +00:00
Ulrich Weigand
0dd44327b0 [PowerPC] Support absolute branches
There is currently only limited support for the "absolute" variants
of branch instructions.  This patch adds support for the absolute
variants of all branches that are currently otherwise supported.

This requires adding new fixup types so that the correct variant
of relocation type can be selected by the object writer.

While the compiler will continue to usually choose the relative
branch variants, this will allow the asm parser to fully support
the absolute branches, with either immediate (numerical) or
symbolic target addresses.

No change in code generation intended.

llvm-svn: 184721
2013-06-24 11:03:33 +00:00
Ulrich Weigand
19b0f3dd0c [PowerPC] Support bd(n)zl and bd(n)zlrl
This adds support for the bd(n)zl and bd(n)zlrl instructions.
The patterns are currently used for the asm parser only.

llvm-svn: 184720
2013-06-24 11:02:38 +00:00
Ulrich Weigand
5c11c4d795 [PowerPC] Support b(cond)l in the asm parser
This patch adds support for the conditional variants of bl.
The pattern is currently used by the asm parser only.

llvm-svn: 184719
2013-06-24 11:02:19 +00:00
Ulrich Weigand
3a0dd840c3 [PowerPC] Support blrl and variants in the asm parser
This patch adds support for blrl and its conditional variants.
The patterns are (currently) used for the asm parser only.

llvm-svn: 184718
2013-06-24 11:01:55 +00:00
Vladimir Medic
4c032a5386 This patch introduces RegisterOperand class into Mips FPU instruction definitions and adds dedicated parser methods to MipsAsmParser. It is the first in a series of patches that should fix the problems with parsing Mips FPU instructions and optimize the code in MipsAsmParser.
llvm-svn: 184716
2013-06-24 10:05:34 +00:00
Michael Gottesman
a893ca16f4 [APFloat] Added support for parsing float strings which contain {inf,-inf,NaN,-NaN}.
llvm-svn: 184713
2013-06-24 09:58:05 +00:00
Michael Gottesman
82b2233f5f [APFloat] Added make{Zero,Inf} methods and implemented get{Zero,Inf} on top of them.
llvm-svn: 184712
2013-06-24 09:58:02 +00:00
Michael Gottesman
9b847e431c [APFloat] Removed a assert from significandParts() which says that one can only access the significand of FiniteNonZero/NaN floats.
The method significandParts() is a helper method meant to ease access to
APFloat's significand by allowing the user to not need to be aware of whether or
not the APFloat is using memory allocated in the instance itself or in an
external array.

This assert says that one can only access the significand of FiniteNonZero/NaN
floats. This makes it cumbersome and more importantly dangerous when one wishes
to zero out the significand of a zero/infinity value since one will have to deal
with the aforementioned quandary related to how the memory in APFloat is
allocated.

llvm-svn: 184711
2013-06-24 09:57:59 +00:00
Michael Gottesman
181a1cd575 [APFloat] Rename macro convolve => PackCategoriesIntoKey so that it is clear what APFloat is actually using said macro for.
In the context of APFloat, seeing a macro called convolve suggests that APFloat
is using said value in some sort of convolution somewhere in the source code.
This is misleading.

I also added a documentation comment to the macro.

llvm-svn: 184710
2013-06-24 09:57:57 +00:00
Amaury de la Vieuville
550e6ef18f ARM: check predicate bits for thumb instructions
When encoded to thumb, VFP instruction and VMOV/VDUP between scalar and
core registers, must have their predicate bit to 0b1110.

llvm-svn: 184707
2013-06-24 09:15:01 +00:00
Amaury de la Vieuville
37b2270352 ARM: rGPR is meant to be unpredictable, not undefined
llvm-svn: 184706
2013-06-24 09:14:54 +00:00
Andrew Trick
716b547d13 Temporarily enable MI-Sched on X86.
Sorry for the unit test churn. I'll try to make the change permanently
next time.

llvm-svn: 184705
2013-06-24 09:13:20 +00:00
Amaury de la Vieuville
5a373a526e ARM: fix thumb1 nop decoding
In thumb1, NOP is a pseudo-instruction equivalent to mov r8, r8.
However the disassembler should not use this alias.

llvm-svn: 184703
2013-06-24 09:11:53 +00:00
Amaury de la Vieuville
6eecd3f2cb ARM: fix IT decoding
mask == 0 -> UNPRED

llvm-svn: 184702
2013-06-24 09:11:45 +00:00
Amaury de la Vieuville
0d7ac788f2 ARM: enable decoding of pc-relative PLD/PLI
llvm-svn: 184701
2013-06-24 09:11:38 +00:00
Chandler Carruth
9788884067 Add a flag to defer vectorization into a phase after the inliner and its
CGSCC pass manager. This should insulate the inlining decisions from the
vectorization decisions, however it may have both compile time and code
size problems so it is just an experimental option right now.

Adding this based on a discussion with Arnold and it seems at least
worth having this flag for us to both run some experiments to see if
this strategy is workable. It may solve some of the regressions seen
with the loop vectorizer.

llvm-svn: 184698
2013-06-24 07:21:47 +00:00
Arnold Schwaighofer
f022b11b08 Revert "LoopVectorize: Use the dependence test utility class"
This reverts commit cbfa1ca993363ca5c4dbf6c913abc957c584cbac.

We are seeing a stage2 and stage3 miscompare on some dragonegg bots.

llvm-svn: 184690
2013-06-24 06:10:41 +00:00
Michael Gottesman
21ef64bbfd [APFloat] Rename llvm::exponent_t => llvm::APFloat::ExponentType.
exponent_t is only used internally in APFloat and no exponent_t values are
exposed via the APFloat API. In light of such conditions it does not make any
sense to gum up the llvm namespace with said type. Plus it makes it clearer that
exponent_t is associated with APFloat.

llvm-svn: 184686
2013-06-24 04:06:23 +00:00
Arnold Schwaighofer
c49cd1a668 LoopVectorize: Use the dependence test utility class
We now no longer need alias analysis - the cases that alias analysis would
handle are now handled as accesses with a large dependence distance.

We can now vectorize loops with simple constant dependence distances.

  for (i = 8; i < 256; ++i) {
    a[i] = a[i+4] * a[i+8];
  }

  for (i = 8; i < 256; ++i) {
    a[i] = a[i-4] * a[i-8];
  }

We would be able to vectorize about 200 more loops (in many cases the cost model
instructs us no to) in the test suite now. Results on x86-64 are a wash.

I have seen one degradation in ammp. Interestingly, the function in which we
now vectorize a loop is never executed so we probably see some instruction
cache effects. There is a 2% improvement in h264ref. There is one or the other
TSCV loop kernel that speeds up.

radar://13681598

llvm-svn: 184685
2013-06-24 03:55:48 +00:00
Arnold Schwaighofer
f9828b092b LoopVectorize: Add utility class for checking dependency among accesses
This class checks dependences by subtracting two Scalar Evolution access
functions allowing us to catch very simple linear dependences.

The checker assumes source order in determining whether vectorization is safe.
We currently don't reorder accesses.
Positive true dependencies need to be a multiple of VF otherwise we impede
store-load forwarding.

llvm-svn: 184684
2013-06-24 03:55:45 +00:00
Arnold Schwaighofer
67714fedcd LoopVectorize: Add utility class for building sets of dependent accesses
Sets of dependent accesses are built by unioning sets based on underlying
objects. This class will be used by the upcoming dependence checker.

llvm-svn: 184683
2013-06-24 03:55:44 +00:00
Nadav Rotem
6c2ae14dc5 SLP Vectorizer: Add support for vectorizing parts of the tree.
Untill now we detected the vectorizable tree and evaluated the cost of the
entire tree.  With this patch we can decide to trim-out branches of the tree
that are not profitable to vectorizer.

Also, increase the max depth from 6 to 12. In the worse possible case where all
of the code is made of diamond-shaped graph this can bring the cost to 2**10,
but diamonds are not very common.

llvm-svn: 184681
2013-06-24 02:52:43 +00:00