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Commit Graph

704 Commits

Author SHA1 Message Date
Dale Johannesen
e61886cee4 Add sqrt and powi intrinsics for long double.
llvm-svn: 42423
2007-09-28 01:08:20 +00:00
Evan Cheng
0a3651a70d Rename keyword "modify" -> "implicit".
llvm-svn: 42282
2007-09-25 01:48:59 +00:00
Evan Cheng
859720c33b Add CopyCost to TargetRegisterClass. This specifies the cost of copying a value
between two registers in the specific class.

llvm-svn: 42123
2007-09-19 01:35:01 +00:00
Evan Cheng
33c343e06b Bug fix and minor clean up of generated code.
llvm-svn: 42069
2007-09-17 22:26:41 +00:00
Chris Lattner
9a1b882091 regenerate
llvm-svn: 42036
2007-09-17 17:40:48 +00:00
Dan Gohman
53119779c2 Remove spurious consts. This fixes warnings with compilers that
are strict about such things.

llvm-svn: 41956
2007-09-14 20:08:19 +00:00
Evan Cheng
bd4b11cfa9 Initial support for multi-result patterns:
1.
[(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
 (modify EFLAGS)]
This indicates the source pattern expects the instruction would produce 2 values. The first is the result of the addition. The second is an implicit definition in register EFLAGS.
2.
def : Pat<(parallel (addc GR32:$src1, GR32:$src2), (modify EFLAGS)), ()>
Similar to #1 except this is used for def : Pat patterns.

llvm-svn: 41897
2007-09-12 23:30:14 +00:00
Evan Cheng
8c1086ae63 Allow set operators with multiple destinations, i.e. (set x, y, (op a, b)).
llvm-svn: 41861
2007-09-11 19:52:18 +00:00
Evan Cheng
65df926ced TableGen no longer emit CopyFromReg nodes for implicit results in physical
registers. The scheduler is now responsible for emitting them.

llvm-svn: 41781
2007-09-07 23:59:02 +00:00
Evan Cheng
0973e15ddd Always check the type of node. This prevents situations such as selecting 32-bit rotate target instruction for a 64-bit node when 64-bit pattern is missing.
llvm-svn: 41710
2007-09-04 20:18:28 +00:00
Dan Gohman
b499ea1cf6 Add MVT::fAny for overloading intrinsics on floating-point types.
llvm-svn: 41128
2007-08-16 21:57:19 +00:00
Rafael Espindola
b20b9e985a propagate struct size and alignment of byval arguments to the DAG
llvm-svn: 40986
2007-08-10 14:44:42 +00:00
Chandler Carruth
67d3119773 This resolves a regression of BasicAA which failed to find any memory information for overloaded intrinsics (PR1600). This resolves that issue, and improves the matching scheme to use a BitVector rather than a binary search.
llvm-svn: 40872
2007-08-06 20:57:16 +00:00
Chandler Carruth
00e56b0e81 This is the patch to provide clean intrinsic function overloading support in LLVM. It cleans up the intrinsic definitions and generally smooths the process for more complicated intrinsic writing. It will be used by the upcoming atomic intrinsics as well as vector and float intrinsics in the future.
This also changes the syntax for llvm.bswap, llvm.part.set, llvm.part.select, and llvm.ct* intrinsics. They are automatically upgraded by both the LLVM ASM reader and the bitcode reader. The test cases have been updated, with special tests added to ensure the automatic upgrading is supported.

llvm-svn: 40807
2007-08-04 01:51:18 +00:00
Evan Cheng
8f126e59f5 Added TargetInstrDescriptor::numDefs - num of results.
llvm-svn: 40709
2007-08-02 00:20:17 +00:00
Dan Gohman
75473b49ea More explicit keywords.
llvm-svn: 40589
2007-07-30 14:51:59 +00:00
Chuck Rose III
4a3a018844 VStudio compiler errors and placing Function*->ExFunc map under ManagedStatic control.
This commit fixes two things.  One is a pair of VStudio compiler errors stemming from variables
which defined within the for loop statement and also within the body of the for loop.  I fixed these 
by renaming one of the two variables.  Additionally, I've made the Function*->ExFunc map in 
ExternalFunctions.cpp a ManagedStatic object, so that cleanup will be done on llvm_shutdown.  In repeated
uses of the interpreter, where the same Function* address may get used for completely differnet functions,
this was causing a crash.

llvm-svn: 40558
2007-07-27 18:26:35 +00:00
Dan Gohman
b7c799015b Fix a pasto in a comment.
llvm-svn: 40527
2007-07-26 15:11:00 +00:00
Christopher Lamb
7bef240f69 Have register info provide the inverse mapping of register->superregisters. PR1350
llvm-svn: 40519
2007-07-26 08:01:58 +00:00
Christopher Lamb
9a0d88efde Add target independent MachineInstr's to represent subreg insert/extract in MBB's. PR1350
llvm-svn: 40518
2007-07-26 07:48:21 +00:00
Christopher Lamb
954afaa83f Teach TableGen about the new vector types.
llvm-svn: 40513
2007-07-26 06:41:18 +00:00
Dan Gohman
7428b0796c A minor simplication in the generated code.
llvm-svn: 40479
2007-07-24 22:58:00 +00:00
Evan Cheng
3c78aadb70 No need for noResults anymore.
llvm-svn: 40075
2007-07-20 00:21:23 +00:00
Evan Cheng
8312ed6f77 Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033
2007-07-19 01:14:50 +00:00
Chris Lattner
fe26fdfeaf Work around a bogus gcc 4.2 warning.
llvm-svn: 39993
2007-07-18 04:51:57 +00:00
Dan Gohman
48b2f7992b Eliminate an unused parameter.
llvm-svn: 39828
2007-07-13 20:16:50 +00:00
Evan Cheng
974bb09390 Try committing again. Add OptionalDefOperand. Remove clobbersPred.
llvm-svn: 38498
2007-07-10 18:05:01 +00:00
Evan Cheng
2ecd061c78 ImmutablePredicateOperand is no more.
llvm-svn: 37963
2007-07-06 23:23:38 +00:00
Rafael Espindola
7b3de98989 Add the byval attribute
llvm-svn: 37940
2007-07-06 10:57:03 +00:00
Evan Cheng
9593d4ed73 Refactor code to add initial support for OptionalDefOperand.
llvm-svn: 37933
2007-07-06 01:05:26 +00:00
Evan Cheng
2ce6ccab6d Teach DAGISelEmitter about zero_reg.
llvm-svn: 37900
2007-07-05 07:19:45 +00:00
Evan Cheng
2a4b3f341b Instructions with ImmutablePredicateOperand aren't really predicable since their predicates are fixed at isel time.
llvm-svn: 37899
2007-07-05 07:19:29 +00:00
John Criswell
57e5ed4b5a Convert .cvsignore files
llvm-svn: 37801
2007-06-29 16:35:07 +00:00
Evan Cheng
c8b17dd965 One additional field in TargetRegisterDesc.
llvm-svn: 37760
2007-06-27 17:09:34 +00:00
Evan Cheng
ac10d44736 Add immediate sub-registers.
llvm-svn: 37738
2007-06-26 20:59:16 +00:00
Dan Gohman
9cbc3fb1ab Revert the earlier change that removed the M_REMATERIALIZABLE machine
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).

llvm-svn: 37728
2007-06-26 00:48:07 +00:00
Dan Gohman
550ec9362b Fix a typo in a comment.
llvm-svn: 37727
2007-06-26 00:43:18 +00:00
Chris Lattner
efa46b445c silence warning when assertions are disabled.
llvm-svn: 37654
2007-06-19 06:40:46 +00:00
Dan Gohman
b60d8a92c9 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.

llvm-svn: 37644
2007-06-19 01:48:05 +00:00
Evan Cheng
12b3002673 Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.
llvm-svn: 37643
2007-06-19 01:26:51 +00:00
Christopher Lamb
68017d151b Add support to tablegen for specifying subregister classes on a per register class basis.
llvm-svn: 37572
2007-06-13 22:20:15 +00:00
Evan Cheng
1be50b2f54 Add clobbersPred - instruction that clobbers condition code / register which are used to predicate instructions.
llvm-svn: 37465
2007-06-06 10:14:55 +00:00
Bill Wendling
d2b1274d1b Patches by Chuck Rose to unbreak V Studio builds.
Thanks Chuck!

llvm-svn: 37428
2007-06-04 23:52:59 +00:00
Dan Gohman
4ea79a66c2 Remove the operator<< for MVT::ValueType in preparation for MVT::ValueType
being changed from an enum to an integer type, which can't have a custom
operator<< overload.

llvm-svn: 37412
2007-06-04 16:11:03 +00:00
Reid Spencer
31622dd4a9 The Intrinsic::getDeclaration function's Tys parameter only contains the
types of the iAny types involved in the overloaded intrinsic. Thus, we
can't use the argument number as the index but have to count them separately
in order to index Tys correctly. This patch rectifies this situation.

llvm-svn: 37296
2007-05-22 19:30:31 +00:00
Evan Cheng
ecb8e3dc44 Rename M_PREDICATED to M_PREDICABLE; opcode can be specified isPredicable without having a PredicateOperand.
llvm-svn: 37116
2007-05-16 20:45:24 +00:00
Chris Lattner
39d713e4a5 Fix CodeGen/PowerPC/2007-05-14-InlineAsmSelectCrash.ll, the other recent
patches are also needed.

llvm-svn: 37070
2007-05-15 01:36:44 +00:00
Evan Cheng
f96cf9eab6 Added \!con(a,b) syntax to concatnate two dag fragments.
llvm-svn: 37063
2007-05-15 01:23:24 +00:00
Evan Cheng
34ce8e7297 Mark all (not just the first) predicate operand M_PREDICATE_OPERAND.
llvm-svn: 37061
2007-05-15 01:20:36 +00:00
Evan Cheng
0afaeec496 PredicateOperand related bug fix.
llvm-svn: 37060
2007-05-15 01:19:51 +00:00