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3 Commits

Author SHA1 Message Date
Daniel Sanders
d13fea547a [mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode. 
llvm-svn: 191498
 2013-09-27 10:08:31 +00:00
Daniel Sanders
6d33546b4a [mips][msa] Summarize tests 
Adds a comment to the start of each test summarizing the area the test covers.

llvm-svn: 189465
 2013-08-28 10:02:29 +00:00
Jack Carter
8798c3bae2 [Mips][msa] Added the simple builtins (fadd to ftq) 
Includes:
fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2,
fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin,
fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt,
fsne, fsqr, fsub, ftint_s, ftq

Patch by Daniel Sanders

llvm-svn: 188458
 2013-08-15 13:45:36 +00:00