Evan Cheng
53cb03b583
No more noResults.
...
llvm-svn: 40132
2007-07-21 00:34:19 +00:00
Evan Cheng
8312ed6f77
Change instruction description to split OperandList into OutOperandList and
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InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 01:14:50 +00:00
Dan Gohman
bff1054303
Define the pushq instruction for x86-64.
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llvm-svn: 37625
2007-06-18 14:12:56 +00:00
Chris Lattner
307a29e831
add support for 128-bit integer add/sub
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llvm-svn: 37154
2007-05-17 06:35:11 +00:00
Bill Wendling
d380bc565b
Have MMX registers clobbered in x86-64 too.
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llvm-svn: 36494
2007-04-26 21:06:48 +00:00
Evan Cheng
32c45fa21e
Some AT&T syntax assembler (e.g. Mac OS X) does not recognize the movq alias for i64 <-> XMM moves.
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llvm-svn: 32609
2006-12-15 19:58:58 +00:00
Evan Cheng
5effab79f3
f64 <-> i64 bit_convert using movq in 64-bit mode.
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llvm-svn: 32587
2006-12-14 21:55:39 +00:00
Evan Cheng
4529b8cf2e
Fix a couple of typo's.
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llvm-svn: 32585
2006-12-14 19:46:06 +00:00
Evan Cheng
adeea85f7d
- Switch X86-64 JIT to large code size model.
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- Re-enable some codegen niceties for X86-64 static relocation model codegen.
- Clean ups, etc.
llvm-svn: 32238
2006-12-05 19:50:18 +00:00
Evan Cheng
2c35691a02
- Fix X86-64 JIT by temporarily disabling code that treats GV address as 32-bit
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immediate in small code model. The JIT cannot ensure GV's are placed in the
lower 4G.
- Some preliminary support for large code model.
llvm-svn: 32215
2006-12-05 04:01:03 +00:00
Evan Cheng
456101ebb9
- Use a different wrapper node for RIP-relative GV, etc.
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- Proper support for both small static and PIC modes under X86-64
- Some (non-optimal) support for medium modes.
llvm-svn: 32046
2006-11-30 21:55:46 +00:00
Evan Cheng
62d19fbf98
Fix JIT encoding bugs for shift / rotate by one ops.
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llvm-svn: 31952
2006-11-28 01:28:00 +00:00
Evan Cheng
fc1b3d8bc8
Correct instructions for moving data between GR64 and SSE registers; also correct load i64 / store i64 from v2i64.
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llvm-svn: 31795
2006-11-16 23:33:25 +00:00
Chris Lattner
7c265ad682
remove dead/redundant vars
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llvm-svn: 31435
2006-11-03 23:48:56 +00:00
Evan Cheng
ca66f49574
Add properties to ComplexPattern.
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llvm-svn: 30891
2006-10-11 21:03:53 +00:00
Evan Cheng
d22f3dd3ed
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
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llvm-svn: 30844
2006-10-09 20:57:25 +00:00
Evan Cheng
cfd7b147cf
X86ISD::CMP now produces a chain as well as a flag. Make that the chain
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operand of a conditional branch to allow load folding into CMP / TEST
instructions.
llvm-svn: 30241
2006-09-11 02:19:56 +00:00
Evan Cheng
100e48fe40
Remove TEST64mr. It's same as TEST64rm since and is commutative.
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llvm-svn: 30178
2006-09-08 06:56:55 +00:00
Evan Cheng
15dd42884e
Committing X86-64 support.
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llvm-svn: 30177
2006-09-08 06:48:29 +00:00