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Commit Graph

103835 Commits

Author SHA1 Message Date
Tom Stellard
a6f7eff1ad R600/SI: Refactor the VOP3_32 tablegen class
This will allow us to use a single MachineInstr to represent
instructions which behave the same but have different encodings
on some subtargets.

llvm-svn: 209028
2014-05-16 20:56:47 +00:00
Tom Stellard
724f41cd91 R600/SI: Add a PredicateControl class for managing TableGen predicates
This was inspired by the PredicateControl class in the MIPS backend.

llvm-svn: 209027
2014-05-16 20:56:45 +00:00
Tom Stellard
dd51c2b7f4 R600/SI: Move tablegen patterns away from instruction defs
llvm-svn: 209026
2014-05-16 20:56:44 +00:00
Tom Stellard
caa7274fef R600/SI: Remove unused instruction
llvm-svn: 209025
2014-05-16 20:56:43 +00:00
Tom Stellard
2022c1eb1b R600/SI: Promote f32 SELECT to i32
llvm-svn: 209024
2014-05-16 20:56:41 +00:00
Tom Stellard
9ed79b238d R600/SI: Remove duplicate pattern
llvm-svn: 209023
2014-05-16 20:56:37 +00:00
Reid Kleckner
fd1a7dfe04 Add comdat key field to llvm.global_ctors and llvm.global_dtors
This allows us to put dynamic initializers for weak data into the same
comdat group as the data being initialized.  This is necessary for MSVC
ABI compatibility.  Once we have comdats for guard variables, we can use
the combination to help GlobalOpt fire more often for weak data with
guarded initialization on other platforms.

Reviewers: nlewycky

Differential Revision: http://reviews.llvm.org/D3499

llvm-svn: 209015
2014-05-16 20:39:27 +00:00
Rafael Espindola
f942b6eb61 Fix a warning in builds without asserts.
llvm-svn: 209012
2014-05-16 20:05:08 +00:00
David Blaikie
a844851458 DebugInfo: Add an assert regarding the subprogram in the subprogram map matching the abstract subprogram.
I'm not sure this is how it'll be going forward (I'd rather prefer the
definition to be in the main SP mapping, for various reasons) but this
helps me understand how it is today.

llvm-svn: 209009
2014-05-16 19:42:10 +00:00
Rafael Espindola
c5f7a8c70e Fix most of PR10367.
This patch changes the design of GlobalAlias so that it doesn't take a
ConstantExpr anymore. It now points directly to a GlobalObject, but its type is
independent of the aliasee type.

To avoid changing all alias related tests in this patches, I kept the common
syntax

@foo = alias i32* @bar

to mean the same as now. The cases that used to use cast now use the more
general syntax

@foo = alias i16, i32* @bar.

Note that GlobalAlias now behaves a bit more like GlobalVariable. We
know that its type is always a pointer, so we omit the '*'.

For the bitcode, a nice surprise is that we were writing both identical types
already, so the format change is minimal. Auto upgrade is handled by looking
through the casts and no new fields are needed for now. New bitcode will
simply have different types for Alias and Aliasee.

One last interesting point in the patch is that replaceAllUsesWith becomes
smart enough to avoid putting a ConstantExpr in the aliasee. This seems better
than checking and updating every caller.

A followup patch will delete getAliasedGlobal now that it is redundant. Another
patch will add support for an explicit offset.

llvm-svn: 209007
2014-05-16 19:35:39 +00:00
David Blaikie
5e7d4ec337 DebugInfo: Assume the CU's Subprogram list only contains definitions.
DIBuilder maintains this invariant and the current DwarfDebug code could
end up doing weird things if it contained declarations (such as putting
the definition DIE inside a CU that contained the declaration - this
doesn't seem like a good idea, so rather than adding logic to handle
this case we'll just ban in for now & cross that bridge if we come to
it later).

llvm-svn: 209004
2014-05-16 18:26:53 +00:00
Chad Rosier
c6f45bc281 [ARM64] Increases the Sched Model accuracy for Cortex-A53.
Patch by Dave Estes <cestes@codeaurora.org>
http://reviews.llvm.org/D3769

llvm-svn: 209001
2014-05-16 17:15:33 +00:00
David Majnemer
ef2cb1fc63 InstSimplify: Improve handling of ashr/lshr
Summary:
Analyze the range of values produced by ashr/lshr cst, %V when it is
being used in an icmp.

Reviewers: nicholas

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D3774

llvm-svn: 209000
2014-05-16 17:14:03 +00:00
David Majnemer
186633e0f8 InstSimplify: Optimize using dividend in sdiv
Summary:
The dividend in an sdiv tells us the largest and smallest possible
results.  Use this fact to optimize comparisons against an sdiv with a
constant dividend.

Reviewers: nicholas

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D3795

llvm-svn: 208999
2014-05-16 16:57:04 +00:00
Tilmann Scheller
bbb4083fd8 [ARM64] Fix wrong comment in load/store optimization pass.
ldr x1, [x0, #64]
add x0, x0, #64
 ->
ldr x1, [x0], #64

is not a valid transformation, the correct transformation (and what the code actually does) is:

ldr x1, [x0, #64]
add x0, x0, #64
 ->
ldr x1, [x0, #64]!

llvm-svn: 208998
2014-05-16 16:50:13 +00:00
David Blaikie
82dc713fc3 DwarfDebug: Refactor AT_ranges/AT_high_pc+AT_low_pc emission into helper function.
llvm-svn: 208997
2014-05-16 16:42:40 +00:00
Simon Atanasyan
808d7bc7a0 [yaml2obj][ELF] Add an optional Size field to the YAML section declaration.
Now the only method to configure ELF section's content and size is to assign
a hexadecimal string to the `Content` field. Unfortunately this way is
completely useless when you need to declare a really large section.

To solve this problem this patch adds one more optional field `Size`
to the `RawContentSection` structure. When yaml2obj generates an ELF file
it uses the following algorithm:
1. If both `Content` and `Size` fields are missed create an empty section.
2. If only `Content` field is missed take section length from the `Size`
   field and fill the section by zero.
3. If only `Size` field is missed create a section using data from
   the `Content` field.
4. If both `Content` and `Size` fields are provided validate that the `Size`
   value is not less than size of `Content` data. Than take section length
   from the `Size`, fill beginning of the section by `Content` and the rest
   by zero.

Examples
--------
* Create a section 0x10000 bytes long filled by zero
  Name: .data
  Type: SHT_PROGBITS
  Flags: [ SHF_ALLOC ]
  Size: 0x10000

* Create a section 0x10000 bytes long starting from 'CA' 'FE' 'BA' 'BE'
  Name: .data
  Type: SHT_PROGBITS
  Flags: [ SHF_ALLOC ]
  Content: CAFEBABE
  Size: 0x10000

The patch reviewed by Michael Spencer.

llvm-svn: 208995
2014-05-16 16:01:00 +00:00
James Molloy
068abd8acc Re-enable inline memcpy expansion for Thumb1.
Patch by Moritz Roth!

llvm-svn: 208994
2014-05-16 14:24:22 +00:00
Rafael Espindola
9ac6a92661 Small dyn_cast and auto cleanup.
llvm-svn: 208993
2014-05-16 14:22:33 +00:00
James Molloy
a4b2ec478f Fix the Load/Store optimization pass to work with Thumb1.
Patch by Moritz Roth!

llvm-svn: 208992
2014-05-16 14:14:30 +00:00
James Molloy
f2173e4edc Enable the Load/Store optimization pass for Thumb1 but make it return immediately for now.
Patch by Moritz Roth!

llvm-svn: 208991
2014-05-16 14:11:38 +00:00
James Molloy
99a2eb4b4d Fix a few comment typos and style issues.
Patch by Moritz Roth!

llvm-svn: 208990
2014-05-16 14:08:46 +00:00
Zoran Jovanovic
cd26b8ebb7 [mips][mips64r6] Add SELEQZ and SELNEZ instructions
Differential Revision: http://reviews.llvm.org/D3743

llvm-svn: 208987
2014-05-16 13:40:57 +00:00
Rafael Espindola
7cf05b14cd Change the GlobalAlias constructor to look a bit more like GlobalVariable.
This is part of the fix for pr10367. A GlobalAlias always has a pointer type,
so just have the constructor build the type.

llvm-svn: 208983
2014-05-16 13:34:04 +00:00
Zoran Jovanovic
a0d70f863c [mips][mips64r6] Add Compact indexed jumps.
Differential Revision: http://reviews.llvm.org/D3707

llvm-svn: 208981
2014-05-16 13:19:46 +00:00
Yaron Keren
a414154d8e Fix hardcoded slash to native path seperator which was exposed from llvm::sys::path.
http://reviews.llvm.org/D3687

llvm-svn: 208980
2014-05-16 13:16:30 +00:00
Rafael Espindola
6d40091c3c Revert "Implement global merge optimization for global variables."
This reverts commit r208934.

The patch depends on aliases to GEPs with non zero offsets. That is not
supported and fairly broken.

The good news is that GlobalAlias is being redesigned and will have support
for offsets, so this patch should be a nice match for it.

llvm-svn: 208978
2014-05-16 13:02:18 +00:00
Zoran Jovanovic
893ce6bcf7 [mips][mips64r6] Add Compact zero-compare branch-and-link instructions
Differential Revision: http://reviews.llvm.org/D3718

llvm-svn: 208977
2014-05-16 12:27:19 +00:00
Stepan Dyatkovskiy
8ade7d0d73 MergeFunctions Pass, introduced total ordering among GEP operations.
Patch replaces old isEquivalentGEP implementation, and changes type of
comparison result from bool (equal or not) to {-1, 0, 1} (less, equal, greater).

This patch belongs to patch series that improves MergeFunctions
performance time from O(N*N) to O(N*log(N)).

llvm-svn: 208976
2014-05-16 11:55:02 +00:00
NAKAMURA Takumi
1942097cb7 MC: Add DwarfTypesDWOSection also to MCCOFF.
llvm-svn: 208975
2014-05-16 11:14:51 +00:00
Zoran Jovanovic
aecb4a7162 [mips][mips64r6] Add compact branch instructions
Differential Revision: http://reviews.llvm.org/D3691

llvm-svn: 208974
2014-05-16 11:03:45 +00:00
Stepan Dyatkovskiy
e456ffe9bc MergeFunctions Pass, introduced total ordering among operations.
Patch replaces old isEquivalentOperation implementation, and changes type of
comparison result from bool (equal or not) to {-1, 0, 1} (less, equal, greater).

This patch belongs to patch series that improves MergeFunctions
performance time from O(N*N) to O(N*log(N)).

llvm-svn: 208973
2014-05-16 11:02:22 +00:00
Zoran Jovanovic
9a1f497ab9 [mips][mips64r6] Add LWPC and LWUPC instructions
Differential Revision: http://reviews.llvm.org/D3788

llvm-svn: 208971
2014-05-16 10:27:10 +00:00
Zoran Jovanovic
e8fbba2fe8 [mips][mips64r6] Add Floating Point Compare setting Mask - CMP.condn.fmt
Differential Revision: http://reviews.llvm.org/D3750

llvm-svn: 208970
2014-05-16 09:48:29 +00:00
Tim Northover
31e1362588 TableGen: fix operand counting for aliases
TableGen has a fairly dubious heuristic to decide whether an alias should be
printed: does the alias have lest operands than the real instruction. This is
bad enough (particularly with no way to override it), but it should at least be
calculated consistently for both strings.

This patch implements that logic: first get the *correct* string for the
variant, in the same way as the Matcher, without guessing; then count the
number of whitespace chars.

There are basically 4 changes this brings about after the previous
commits; all of these appear to be good, so I have changed the tests:

+ ARM64: we print "neg X, Y" instead of "sub X, xzr, Y".
+ ARM64: we skip implicit "uxtx" and "uxtw" modifiers.
+ Sparc: we print "mov A, B" instead of "or %g0, A, B".
+ Sparc: we print "fcmpX A, B" instead of "fcmpX %fcc0, A, B"

llvm-svn: 208969
2014-05-16 09:42:04 +00:00
Tim Northover
a52367cca6 ARM64: disable printing of "fcmXY ..., #0" aliases
The canonical syntax is "fcmXY ..., #0.0".

This will be tested when the TableGen "should I print this Alias" heuristic is
fixed (very soon).

llvm-svn: 208968
2014-05-16 09:41:48 +00:00
Tim Northover
7dfb58559c AArch64: disable printing of add/sub alias
This alias appears not to have an appropriate PrintMethod. Normally, I'd look
into it, but since AArch64 is disappearing soon it's probably not worth it.

This will be tested when the TableGen "should I print this Alias" heuristic is
fixed (very soon).

llvm-svn: 208967
2014-05-16 09:41:43 +00:00
Tim Northover
33e6c879f8 Sparc: disable printing of jmp/call aliases (C++ does it)
These aliases are handled entirely in C++ and only having TableGen InstAliases
for some of them was confusing LLVM.

This will be tested when the TableGen "should I print this Alias" heuristic is
fixed (very soon).

llvm-svn: 208966
2014-05-16 09:41:39 +00:00
Tim Northover
4657cf85a5 Sparc: disable printing on longer "brX,pt" aliases
This will be tested when the TableGen "should I print this Alias" heuristic is
fixed (very soon).

llvm-svn: 208965
2014-05-16 09:41:35 +00:00
Tim Northover
9e02604274 Mips: don't print subu alias for addiu
Certainly not without having a custom PrintMethod to invert the immediate
beforehand. But probably not at all.

This will be tested when the TableGen "should I print this Alias" heuristic is
fixed (very soon).

llvm-svn: 208964
2014-05-16 09:41:30 +00:00
Tim Northover
25b5918f36 X86: disable printing of bare "mov" aliases
In AT&T syntax, we should probably print the full "movl" or "movw". TableGen
used to ignore these aliases because it was miscounting the number of operands.
This fixes the issue.

This will be tested when the TableGen "should I print this Alias"
heuristic is fixed (very soon).

llvm-svn: 208963
2014-05-16 09:41:26 +00:00
Tim Northover
4736478963 AArch64: disable printing of MOV -> MOVZ aliases
Actually, MOV sometimes is canonical, but for now this is a better
approximation than what's there.

This will be tested when the TableGen "should I print this Alias" heuristic is
fixed (very soon).

llvm-svn: 208962
2014-05-16 09:41:21 +00:00
Tim Northover
a1a9dc1522 ARM64: disable printing of swapped compare-mask aliases
You can perform (say) an fcmle operation by swapping the operands on an fcmge,
but it shouldn't be printed like that.

This will be tested when the TableGen "should I print this Alias" heuristic is
fixed (very soon).

llvm-svn: 208961
2014-05-16 09:41:16 +00:00
Tim Northover
73da7b061d ARM64: disable printing of LDUR -> LDR aliases
We accept "ldr w3, [x1, #-1]" as a convenience, but we should still print the
canonical "ldur" form.

This will be tested when the TableGen "should I print this Alias" heuristic is
fixed (very soon).

llvm-svn: 208960
2014-05-16 09:41:12 +00:00
Tim Northover
ed69e87c09 ARM64: give TST aliases priority over ANDS.
If an ANDS instruction has Rd == ZR it should be printed as TST since
its only effect is on the flags register NZCV.

This will be tested when the TableGen "should I print this Alias"
heuristic is fixed (very soon).

llvm-svn: 208959
2014-05-16 09:41:08 +00:00
Tim Northover
a817d71dd4 ARM64: give MOV priority over shorter ORR when printing aliases.
MOV is almost always the right thing to print if possile. People understand it.

This will be tested when the TableGen "should I print this Alias" heuristic is
fixed (very soon).

llvm-svn: 208958
2014-05-16 09:41:03 +00:00
Tim Northover
e0ce8a79e2 ARM64: give NEG priority over SUB when printing aliases.
For example, the full instruction "sub w0, wzr, w1, uxtw" could print as either
"neg w0, w1" or "sub w0, wzr, w1". The former is better.

This will be tested when the TableGen "should I print this Alias" heuristic is
fixed (very soon).

llvm-svn: 208957
2014-05-16 09:40:58 +00:00
Tim Northover
752863fabb ARM64: disable printing of "lslv" type aliases
You can write "lslv w0, w1, w2" (probably for legacy reasons), but it should be
printed as simply "lsl".

This will be tested when the TableGen "should I print this Alias" heuristic is
fixed (very soon).

llvm-svn: 208956
2014-05-16 09:40:52 +00:00
Hao Liu
effb003c48 [ARM64]Implement NEON post-increment LD1(lane) and post-increment LD1R.
llvm-svn: 208955
2014-05-16 09:39:02 +00:00
Stepan Dyatkovskiy
f2d01849f9 MergeFunctions Pass, introduced total ordering among function attributes.
This patch belongs to patch series that improves MergeFunctions
performance time from O(N*N) to O(N*log(N)).

llvm-svn: 208953
2014-05-16 08:55:34 +00:00