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Commit Graph

95164 Commits

Author SHA1 Message Date
Akira Hatanaka
a80bdd3ab0 [mips] Add support for mfhc1 and mthc1.
llvm-svn: 188848
2013-08-20 23:47:25 +00:00
Akira Hatanaka
a69a24ff08 [mips] Add support for calling convention CC_MipsO32_FP64, which is used when the
size of floating point registers is 64-bit.

Test case will be added when support for mfhc1 and mthc1 is added.

llvm-svn: 188847
2013-08-20 23:38:40 +00:00
Akira Hatanaka
4a39cd048c [mips] Remove predicates that were incorrectly or unnecessarily added.
llvm-svn: 188845
2013-08-20 23:21:55 +00:00
Jakub Staszak
b5370ddc88 Add some constantness.
llvm-svn: 188844
2013-08-20 23:04:15 +00:00
Bill Wendling
f0d4bdaaa3 Use -disable-output and to suppress output and don't use a temporary file unless we need one.
llvm-svn: 188843
2013-08-20 23:00:25 +00:00
Akira Hatanaka
47043cf547 [mips] Define register class FGRH32 for the high half of the 64-bit floating
point registers. We will need this register class later when we add
definitions for instructions mfhc1 and mthc1. Also, remove sub-register indices
sub_fpeven and sub_fpodd and use sub_lo and sub_hi instead.

llvm-svn: 188842
2013-08-20 22:58:56 +00:00
Jakub Staszak
7abd94505d Fix include guards.
llvm-svn: 188841
2013-08-20 22:52:02 +00:00
Arnold Schwaighofer
276cfe784a SLPVectorizer: Fix invalid iterator errors
Update iterator when the SLP vectorizer changes the instructions in the basic
block by restarting the traversal of the basic block.

Patch by Yi Jiang!

Fixes PR 16899.

llvm-svn: 188832
2013-08-20 21:21:45 +00:00
Matt Arsenault
474ae7ebd0 Teach ConstantFolding about pointer address spaces
llvm-svn: 188831
2013-08-20 21:20:04 +00:00
Akira Hatanaka
191591d4eb [mips] Resolve register classes dynamically using ptr_rc to reduce the number of
load/store instructions defined. Previously, we were defining load/store
instructions for each pointer size (32 and 64-bit), but now we need just one
definition.

llvm-svn: 188830
2013-08-20 21:08:22 +00:00
Reed Kotler
3e323b240e Add an option which permits the user to specify using a bitmask, that various
functions be compiled as mips32, without having to add attributes. This
is useful in certain situations where you don't want to have to edit the
function attributes in the source. For now it's only an option used for
the compiler developers when debugging the mips16 port.

llvm-svn: 188826
2013-08-20 20:53:09 +00:00
Akira Hatanaka
ea8d1c863e [mips] Guard micromips instructions with predicate InMicroMips. Also, fix
assembler predicate HasStdEnd so that it is false when the target is micromips.

llvm-svn: 188824
2013-08-20 20:46:51 +00:00
Jim Grosbach
343f1fbc39 ARM: Fix fast-isel copy/paste-o.
Update testcase to be more careful about checking register
values. While regexes are general goodness for these sorts of
testcases, in this example, the registers are constrained by
the calling convention, so we can and should check their
explicit values.

rdar://14779513

llvm-svn: 188819
2013-08-20 19:12:42 +00:00
Andrew Kaylor
9e0cc76cbd Still more MCJIT PIC test XFAILs
llvm-svn: 188815
2013-08-20 18:13:48 +00:00
Andrew Kaylor
bfbe500b28 Clarifying two MCJIT PIC tests as XFAIL on i686-pc-linux
llvm-svn: 188814
2013-08-20 17:01:35 +00:00
Andrew Kaylor
c9806bde8d Removing duplicate XFAIL markers
llvm-svn: 188812
2013-08-20 16:42:22 +00:00
Andrew Kaylor
e686f825de Marking two more MCJIT PIC tests as XFAIL on i686
llvm-svn: 188808
2013-08-20 15:47:04 +00:00
Andrew Kaylor
e10f756aa1 Marking MCJIT PIC tests as XFAIL on arm
llvm-svn: 188807
2013-08-20 15:36:04 +00:00
Vladimir Medic
4271ac93aa Fix style issues in AsmParser.cpp
llvm-svn: 188798
2013-08-20 13:33:18 +00:00
Elena Demikhovsky
f09dad5d90 AVX-512: Added more patterns for VMOVSS, VMOVSD, VMOVD, VMOVQ
llvm-svn: 188786
2013-08-20 11:00:29 +00:00
Daniel Sanders
30561c36b8 [mips][msa] Removed fcge, fcgt, fsge, fsgt
These instructions were present in a draft spec but were removed before
publication.

llvm-svn: 188782
2013-08-20 09:41:47 +00:00
Richard Sandiford
7aca0c4227 [SystemZ] Update README
We now use MVST, CLST and SRST for the obvious cases.

llvm-svn: 188781
2013-08-20 09:40:35 +00:00
Richard Sandiford
add1a68f21 [SystemZ] Use SRST to optimize memchr
SystemZTargetLowering::emitStringWrapper() previously loaded the character
into R0 before the loop and made R0 live on entry.  I'd forgotten that
allocatable registers weren't allowed to be live across blocks at this stage,
and it confused LiveVariables enough to cause a miscompilation of f3 in
memchr-02.ll.

This patch instead loads R0 in the loop and leaves LICM to hoist it
after RA.  This is actually what I'd tried originally, but I went for
the manual optimisation after noticing that R0 often wasn't being hoisted.
This bug forced me to go back and look at why, now fixed as r188774.

We should also try to optimize null checks so that they test the CC result
of the SRST directly.  The select between null and the SRST GPR result could
then usually be deleted as dead.

llvm-svn: 188779
2013-08-20 09:38:48 +00:00
Benjamin Kramer
f2cb55f757 memcmp is not a valid way to compare structs with padding in them.
llvm-svn: 188778
2013-08-20 09:27:31 +00:00
Daniel Sanders
91c40d80de [mips][msa] Added insve
llvm-svn: 188777
2013-08-20 09:22:54 +00:00
Richard Sandiford
6a0b1638b4 Fix test typo and add usual "br %r14" test
llvm-svn: 188775
2013-08-20 09:14:46 +00:00
Richard Sandiford
fcd54a3b89 Fix overly pessimistic shortcut in post-RA MachineLICM
Post-RA LICM keeps three sets of registers: PhysRegDefs, PhysRegClobbers
and TermRegs.  When it sees a definition of R it adds all aliases of R
to the corresponding set, so that when it needs to test for membership
it only needs to test a single register, rather than worrying about
aliases there too.  E.g. the final candidate loop just has:

    unsigned Def = Candidates[i].Def;
    if (!PhysRegClobbers.test(Def) && ...) {

to test whether register Def is multiply defined.

However, there was also a shortcut in ProcessMI to make sure we didn't
add candidates if we already knew that they would fail the final test.
This shortcut was more pessimistic than the final one because it
checked whether _any alias_ of the defined register was multiply defined.
This is too conservative for targets that define register pairs.
E.g. on z, R0 and R1 are sometimes used as a pair, so there is a
128-bit register that aliases both R0 and R1.  If a loop used
R0 and R1 independently, and the definition of R0 came first,
we would be able to hoist the R0 assignment (because that used
the final test quoted above) but not the R1 assignment (because
that meant we had two definitions of the paired R0/R1 register
and would fail the shortcut in ProcessMI).

This patch just uses the same check for the ProcessMI shortcut as
we use in the final candidate loop.

llvm-svn: 188774
2013-08-20 09:11:13 +00:00
Tim Northover
cec1079024 ARM: implement some simple f64 materializations.
Previously we used a const-pool load for virtually all 64-bit floating values.
Actually, we can get quite a few common values (including 0.0, 1.0) via "vmov"
instructions of one stripe or another.

llvm-svn: 188773
2013-08-20 08:57:11 +00:00
Michael Gottesman
7bcc2da0c0 [stackprotector] Small cleanup.
llvm-svn: 188772
2013-08-20 08:56:28 +00:00
Michael Gottesman
2bc9b68fb8 [stackprotector] Small Bit of computation hoisting.
llvm-svn: 188771
2013-08-20 08:56:26 +00:00
Michael Gottesman
1bad711e58 [stackprotector] Added significantly longer comment to FindPotentialTailCall to make clear its relationship to llvm::isInTailCallPosition.
llvm-svn: 188770
2013-08-20 08:56:23 +00:00
Michael Gottesman
708165a1b3 Removed trailing whitespace.
llvm-svn: 188769
2013-08-20 08:46:16 +00:00
Michael Gottesman
780a56c825 [stackprotector] Removed stale TODO.
llvm-svn: 188768
2013-08-20 08:46:13 +00:00
Daniel Sanders
15341e9a12 [mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v
llvm-svn: 188767
2013-08-20 08:38:21 +00:00
Michael Gottesman
ba9e36102b [stackprotector] Added support for emitting the llvm intrinsic stack protector check.
rdar://13935163

llvm-svn: 188766
2013-08-20 08:36:53 +00:00
Michael Gottesman
d2ede9d0a0 [stackprotector] Refactor out the end of isInTailCallPosition into the function returnTypeIsEligibleForTailCall.
This allows me to use returnTypeIsEligibleForTailCall in the stack protector pass.

rdar://13935163

llvm-svn: 188765
2013-08-20 08:36:50 +00:00
Michael Gottesman
c760b9c3d7 Remove unused variables that crept in.
llvm-svn: 188761
2013-08-20 07:17:27 +00:00
Michael Gottesman
9da49efd0a Teach selectiondag how to handle the stackprotectorcheck intrinsic.
Previously, generation of stack protectors was done exclusively in the
pre-SelectionDAG Codegen LLVM IR Pass "Stack Protector". This necessitated
splitting basic blocks at the IR level to create the success/failure basic
blocks in the tail of the basic block in question. As a result of this,
calls that would have qualified for the sibling call optimization were no
longer eligible for optimization since said calls were no longer right in
the "tail position" (i.e. the immediate predecessor of a ReturnInst
instruction).

Then it was noticed that since the sibling call optimization causes the
callee to reuse the caller's stack, if we could delay the generation of
the stack protector check until later in CodeGen after the sibling call
decision was made, we get both the tail call optimization and the stack
protector check!

A few goals in solving this problem were:

  1. Preserve the architecture independence of stack protector generation.

  2. Preserve the normal IR level stack protector check for platforms like
     OpenBSD for which we support platform specific stack protector
     generation.

The main problem that guided the present solution is that one can not
solve this problem in an architecture independent manner at the IR level
only. This is because:

  1. The decision on whether or not to perform a sibling call on certain
     platforms (for instance i386) requires lower level information
     related to available registers that can not be known at the IR level.

  2. Even if the previous point were not true, the decision on whether to
     perform a tail call is done in LowerCallTo in SelectionDAG which
     occurs after the Stack Protector Pass. As a result, one would need to
     put the relevant callinst into the stack protector check success
     basic block (where the return inst is placed) and then move it back
     later at SelectionDAG/MI time before the stack protector check if the
     tail call optimization failed. The MI level option was nixed
     immediately since it would require platform specific pattern
     matching. The SelectionDAG level option was nixed because
     SelectionDAG only processes one IR level basic block at a time
     implying one could not create a DAG Combine to move the callinst.

To get around this problem a few things were realized:

  1. While one can not handle multiple IR level basic blocks at the
     SelectionDAG Level, one can generate multiple machine basic blocks
     for one IR level basic block. This is how we handle bit tests and
     switches.

  2. At the MI level, tail calls are represented via a special return
     MIInst called "tcreturn". Thus if we know the basic block in which we
     wish to insert the stack protector check, we get the correct behavior
     by always inserting the stack protector check right before the return
     statement. This is a "magical transformation" since no matter where
     the stack protector check intrinsic is, we always insert the stack
     protector check code at the end of the BB.

Given the aforementioned constraints, the following solution was devised:

  1. On platforms that do not support SelectionDAG stack protector check
     generation, allow for the normal IR level stack protector check
     generation to continue.

  2. On platforms that do support SelectionDAG stack protector check
     generation:

    a. Use the IR level stack protector pass to decide if a stack
       protector is required/which BB we insert the stack protector check
       in by reusing the logic already therein. If we wish to generate a
       stack protector check in a basic block, we place a special IR
       intrinsic called llvm.stackprotectorcheck right before the BB's
       returninst or if there is a callinst that could potentially be
       sibling call optimized, before the call inst.

    b. Then when a BB with said intrinsic is processed, we codegen the BB
       normally via SelectBasicBlock. In said process, when we visit the
       stack protector check, we do not actually emit anything into the
       BB. Instead, we just initialize the stack protector descriptor
       class (which involves stashing information/creating the success
       mbbb and the failure mbb if we have not created one for this
       function yet) and export the guard variable that we are going to
       compare.

    c. After we finish selecting the basic block, in FinishBasicBlock if
       the StackProtectorDescriptor attached to the SelectionDAGBuilder is
       initialized, we first find a splice point in the parent basic block
       before the terminator and then splice the terminator of said basic
       block into the success basic block. Then we code-gen a new tail for
       the parent basic block consisting of the two loads, the comparison,
       and finally two branches to the success/failure basic blocks. We
       conclude by code-gening the failure basic block if we have not
       code-gened it already (all stack protector checks we generate in
       the same function, use the same failure basic block).

llvm-svn: 188755
2013-08-20 07:00:16 +00:00
Craig Topper
3bda7ba32d Fix formatting. No functional change.
llvm-svn: 188746
2013-08-20 05:23:59 +00:00
Craig Topper
0c2625083b Add AVX-512 and related features to the CPUID detection code.
llvm-svn: 188745
2013-08-20 05:22:42 +00:00
Craig Topper
94afe57f94 Move AVX and non-AVX replication inside a couple multiclasses to avoid repeating each instruction for both individually.
llvm-svn: 188743
2013-08-20 04:24:14 +00:00
Craig Topper
77fb9fd06a Add an error check for a typo I accidentally made in a td file that caused an assert to fire.
llvm-svn: 188742
2013-08-20 04:22:09 +00:00
Bill Schmidt
178a1ca418 [PowerPC] More refactoring prior to real PPC emitPrologue/Epilogue changes.
(Patch committed on behalf of Mark Minich, whose log entry follows.)

This is a continuation of the refactorings performed in svn rev 188573
(see that rev's comments for more detail).

This is my stage 2 refactoring: I combined the emitPrologue() &
emitEpilogue() PPC32 & PPC64 code into a single flow, simplifying a
lot of the code since in essence the PPC32 & PPC64 code generation
logic is the same, only the instruction forms are different (in most
cases). This simplification is necessary because my functional changes
(yet to come) add significant complexity, and without the
simplification of my stage 2 refactoring, the overall complexity of
both emitPrologue() & emitEpilogue() would have become almost
intractable for most mortal programmers (like me).

This submission was intended to be a pure refactoring (no functional
changes whatsoever). However, in the process of combining the PPC32 &
PPC64 flows, I spotted a difference that I believe is a bug (see svn
rev 186478 line 863, or svn rev 188573 line 888): This line appears to
be restoring the BP with the original FP content, not the original BP
content. When I merged the 32-bit and 64-bit code, I used the
corresponding code from the 64-bit flow, which I believe uses the
correct offset (BPOffset) for this operation.

llvm-svn: 188741
2013-08-20 03:12:23 +00:00
Andrew Kaylor
745a59aca5 Marking MCJIT PIC tests as XFAIL on AArch64
llvm-svn: 188740
2013-08-20 01:50:50 +00:00
Venkatraman Govindaraju
87eaa9ee17 [Sparc] Use HWEncoding instead of unused Num field in Sparc register definitions. Also, correct the definitions of RETL and RET instructions.
llvm-svn: 188738
2013-08-20 01:26:14 +00:00
Andrew Kaylor
17dcfe14bc Fixing XPASSes among MCJIT PIC test on i686
llvm-svn: 188736
2013-08-20 00:37:33 +00:00
Andrew Kaylor
3653cb94e4 Second attempt to mark Large/PIC MCJIT test as XFAIL for PowerPC64
llvm-svn: 188735
2013-08-20 00:22:03 +00:00
Andrew Kaylor
bb483e15f1 Marking two MCJIT PIC tests as XFAIL on Darwin
llvm-svn: 188734
2013-08-20 00:14:50 +00:00
Andrew Kaylor
895491fcf0 Trying again with PIC tests for MCJIT
llvm-svn: 188730
2013-08-19 23:52:53 +00:00
Hal Finkel
8f395a803a Add a llvm.copysign intrinsic
This adds a llvm.copysign intrinsic; We already have Libfunc recognition for
copysign (which is turned into the FCOPYSIGN SDAG node). In order to
autovectorize calls to copysign in the loop vectorizer, we need a corresponding
intrinsic as well.

In addition to the expected changes to the language reference, the loop
vectorizer, BasicTTI, and the SDAG builder (the intrinsic is transformed into
an FCOPYSIGN node, just like the function call), this also adds FCOPYSIGN to a
few lists in LegalizeVector{Ops,Types} so that vector copysigns can be
expanded.

In TargetLoweringBase::initActions, I've made the default action for FCOPYSIGN
be Expand for vector types. This seems correct for all in-tree targets, and I
think is the right thing to do because, previously, there was no way to generate
vector-values FCOPYSIGN nodes (and most targets don't specify an action for
vector-typed FCOPYSIGN).

llvm-svn: 188728
2013-08-19 23:35:46 +00:00