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Commit Graph

11 Commits

Author SHA1 Message Date
Matt Arsenault
be108f1643 R600/SI: Fix moveToVALU when the first operand is VSrc.
Moving into a VSrc doesn't always work, since it could be
replaced with an SGPR later.

llvm-svn: 195042
2013-11-18 20:09:55 +00:00
Tom Stellard
01fa6ad95f R600/SI: Add VReg_96 register class to SIRegisterInfo::hasVGPRs()
This fixes a crash with GNOME settings manager.

llvm-svn: 194836
2013-11-15 18:26:45 +00:00
Tom Stellard
c38302be13 R600/SI: Add support for private address space load/store
Private address space is emulated using the register file with
MOVRELS and MOVRELD instructions.

llvm-svn: 194626
2013-11-13 23:36:50 +00:00
Tom Stellard
90e4344bae R600/SI: Prefer SALU instructions for bit shift operations
All shift operations will be selected as SALU instructions and then
if necessary lowered to VALU instructions in the SIFixSGPRCopies pass.

This allows us to do more operations on the SALU which will improve
performance and is also required for implementing private memory
using indirect addressing, since the private memory pointers must stay
in the scalar registers.

This patch includes some fixes from Matt Arsenault.

llvm-svn: 194625
2013-11-13 23:36:37 +00:00
Matt Arsenault
772ac26492 Make method static
llvm-svn: 194340
2013-11-10 01:04:02 +00:00
Tom Stellard
d407d90f9a R600/SI: Mark the EXEC register as reserved
This prevents the machine verifier from complaining about uses of
an undefined physical register.

Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 192364
2013-10-10 17:11:19 +00:00
Tom Stellard
37ce97cebc R600/SI: Choose the correct MOV instruction for copying immediates
The instruction selector will now try to infer the destination register
so it can decided whether to use V_MOV_B32 or S_MOV_B32 when copying
immediates.

llvm-svn: 188426
2013-08-14 23:24:24 +00:00
Tom Stellard
eab7c786d4 R600/SI: Add more special cases for opcodes to ensureSRegLimit()
Also factor out the register class lookup to its own function.

llvm-svn: 187830
2013-08-06 23:08:18 +00:00
Bill Wendling
aa15a56463 Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.

No functionality change intended.

llvm-svn: 183561
2013-06-07 20:28:55 +00:00
Christian Konig
0560f719ba R600/SI: switch back to RegPressure scheduling
Signed-off-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178021
2013-03-26 14:04:02 +00:00
Tom Stellard
6f17e7033b Add R600 backend
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX

llvm-svn: 169915
2012-12-11 21:25:42 +00:00