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Commit Graph

59216 Commits

Author SHA1 Message Date
Will Schmidt
e3ba962bc2 [patch] bug 15055 Add Unistd.h to OProfileWrapper.cpp
Add #include <unistd.h> to OProfileWrapper.cpp.   This provides the declarations for 'read' and 'close' that are otherwise missing, and result in 'error: <foo> was not declared in this scope'.

This matches the issue as reported in bug 15055 "Can no longer compile LLVM with --with-oprofile"

llvm-svn: 174661
2013-02-07 20:43:33 +00:00
Bill Schmidt
73c6529ed8 Constrain PowerPC autovectorization to fix bug 15041.
Certain vector operations don't vectorize well with the current
PowerPC implementation.  Element insert/extract performs poorly
without VSX support because Altivec requires going through memory.
SREM, UREM, and VSELECT all produce bad scalar code.

There's a lot of work to do for the cost model before
autovectorization will be tuned well, and this is not an attempt to
address the larger problem.

llvm-svn: 174660
2013-02-07 20:33:57 +00:00
Akira Hatanaka
a989d1f25d [mips] Add definition of JALR instruction which has two register operands. Change the
original JALR instruction with one register operand to be a pseudo-instruction.

llvm-svn: 174657
2013-02-07 19:48:00 +00:00
Tom Stellard
075c61683a R600/SI: cleanup VGPR encoding
Remove all the unused code.

Patch by: Christian König

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 174656
2013-02-07 19:39:45 +00:00
Tom Stellard
6d64a9f30f R600/SI: Handle VGPR64 destination in copyPhysReg().
Allows nexuiz to run with radeonsi.

Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 174655
2013-02-07 19:39:43 +00:00
Tom Stellard
ae734a7b57 R600/SI: Add pattern for mul.
20 more little piglits with radeonsi.

Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 174654
2013-02-07 19:39:42 +00:00
Tom Stellard
39fe9a91bc R600/SI: simplify and fix SMRD encoding
The _SGPR variants where wrong.

Patch by: Christian König

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 174653
2013-02-07 19:39:40 +00:00
Tom Stellard
717a555b33 R600/SI: add proper 64bit immediate support v2
v2: rebased on current upstream

Patch by: Christian König

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 174652
2013-02-07 19:39:38 +00:00
Tom Stellard
84202bed28 R600: Add an explicit default processor
This is for the case when no processor is passed to the backend.  This
prevents the

'' is not a recognized processor for this target (ignoring processor)

warning from being generated by clang.

llvm-svn: 174651
2013-02-07 19:39:34 +00:00
Michael Ilseman
45215bd40b Identify and simplify idempotent intrinsics. Test case included.
llvm-svn: 174650
2013-02-07 19:26:05 +00:00
Arnold Schwaighofer
cae839558d Loop Vectorizer: Refactor Memory Cost Computation
We don't want too many classes in a pass and the classes obscure the details. I
was going a little overboard with object modeling here. Replace classes by
generic code that handles both loads and stores.

No functionality change intended.

llvm-svn: 174646
2013-02-07 19:05:21 +00:00
Tom Stellard
a3945f0d83 R600/SI: Use proper instructions for array/shadow samplers.
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 174634
2013-02-07 17:02:14 +00:00
Tom Stellard
d92ee77690 R600/SI: Make sample intrinsic address parameter type overloaded.
Handle vectors of 1 to 16 integers.

Change the intrinsic names to prevent the wrong one from being selected at
runtime due to the overloading.

Patch By: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 174633
2013-02-07 17:02:13 +00:00
Tom Stellard
83ddc0cbee R600/SI: Add basic support for more integer vector types.
v1i32, v2i32, v8i32 and v16i32.

Only add VGPR register classes for integer vector types, to avoid attempts
copying from VGPR to SGPR registers, which is not possible.

Patch By: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 174632
2013-02-07 17:02:09 +00:00
Arnold Schwaighofer
72b584b5de ARM cost model: Add costs for vector selects
Vector selects are cheap on NEON. They get lowered to a vbsl instruction.

radar://13158753

llvm-svn: 174631
2013-02-07 16:10:15 +00:00
Michel Danzer
53ab21d50d R600/SI: Add pattern for flog2
22 more little piglits with radeonsi.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 174615
2013-02-07 14:55:16 +00:00
NAKAMURA Takumi
2ea96df1f0 FDE::dumpHeader(): Forgot to fix one more formatting, ... take two!
Excuse me, I could not test it locally.

llvm-svn: 174614
2013-02-07 14:54:42 +00:00
Tom Stellard
5910576d37 R600: Consolidate sub register indices.
Use sub0-15 everywhere.

Patch by: Michel Dänzerr

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 174610
2013-02-07 14:02:37 +00:00
Tom Stellard
32a764306e R600: Add support for SET*_DX10 instructions
These instructions compare two floating point values and return an
integer true (-1) or false (0) value.

When compiling code generated by the Mesa GLSL frontend, the SET*_DX10
instructions save us four instructions for most branch decisions that
use floating-point comparisons.

llvm-svn: 174609
2013-02-07 14:02:35 +00:00
Tom Stellard
4ecff0777e R600: Fix assembly name for SETGT_INT
llvm-svn: 174607
2013-02-07 14:02:27 +00:00
NAKAMURA Takumi
d33774373d FDE::dumpHeader(): Forgot to fix one more formatting. It affected bigendian hosts.
llvm-svn: 174602
2013-02-07 10:57:42 +00:00
Reed Kotler
8ac7f84606 Make sure we call externals from libraries properly when -static.
For example, when we are doing mips16 hard float or soft float.

llvm-svn: 174583
2013-02-07 04:34:51 +00:00
Sean Silva
6309c4fe22 tblgen: Diagnose duplicate includes.
A double inclusion will pretty much always be an error in TableGen, so
there's no point going on just to die with "def already defined" or
whatnot.

I'm not too thrilled about the "public: ... private: ..." to expose the
DependenciesMapTy, but I really didn't see a better way to keep that
type centralized. It's a smell that indicates that some refactoring is
needed to make this code more loosely coupled.

This should avoid all bugs of the same nature as PR15189.

llvm-svn: 174582
2013-02-07 04:30:39 +00:00
Michael Gottesman
68014cd1fa Moved some comments due to the recent refactoring of ObjCARC.
1. Moved a comment from ObjCARCOpts.cpp -> ObjCARCContract.cpp.
2. Removed a comment from ObjCARCOpts.cpp that was already moved to
ObjCARCAliasAnalysis.h/.cpp.

llvm-svn: 174581
2013-02-07 04:12:57 +00:00
Reed Kotler
b3d71de768 Enable jumps when in -static mode.
llvm-svn: 174580
2013-02-07 03:49:51 +00:00
NAKAMURA Takumi
b493210348 DWARFDebugFrame.cpp: Fix formatting on i686 hosts.
FIXME: Are they really truncated to i32 from i64 unconditionally?
llvm-svn: 174574
2013-02-07 02:02:27 +00:00
Michael Ilseman
27c81fc400 Preserve fast-math flags after reassociation and commutation. Update test cases
llvm-svn: 174571
2013-02-07 01:40:15 +00:00
Owen Anderson
4d8f6634c5 Conditionalize constant folding of math intrinsics on the availability of an implementation on the host. This is a little bit unfortunate, but until someone decides to implement a full libm for APFloat, we don't have a better way to get this functionality.
llvm-svn: 174561
2013-02-07 00:21:34 +00:00
Owen Anderson
93b6c99e55 Signficantly generalize our ability to constant fold floating point intrinsics, including ones on half types.
llvm-svn: 174555
2013-02-06 22:43:31 +00:00
Joe Abbey
6de61a11af Code Custodian (trivial whitespace cleanup)
llvm-svn: 174550
2013-02-06 22:14:06 +00:00
Eric Christopher
19e3875192 Clean up multiple skeleton compile units if we have multiple compile
units coming in.

llvm-svn: 174548
2013-02-06 21:53:56 +00:00
Eric Christopher
9d072d2846 Remove some dead code.
llvm-svn: 174547
2013-02-06 21:53:53 +00:00
Akira Hatanaka
9a19eb22dc [mips] Make NOP a pseudo instruction and expand it to "sll $zero, $zero, 0".
llvm-svn: 174546
2013-02-06 21:50:15 +00:00
Eli Bendersky
1854305220 This is a follow-up on r174446, now taking Atom processors into
account. Atoms use LEA for updating SP in prologs/epilogs, and the
exact LEA opcode depends on the data model.

Also reapplying the test case which was added and then reverted
(because of Atom failures), this time specifying explicitly the CPU in
addition to the triple. The test case now checks all variations (data
mode, cpu Atom vs. Core).

llvm-svn: 174542
2013-02-06 20:43:57 +00:00
Bill Schmidt
93695a5520 PPC calling convention cleanup.
Most of PPCCallingConv.td is used only by the 32-bit SVR4 ABI.  Rename
things to clarify this.  Also delete some code that's been commented out
for a long time.

llvm-svn: 174526
2013-02-06 17:33:58 +00:00
Tom Stellard
386be85491 R600: Support for indirect addressing v4
Only implemented for R600 so far.  SI is missing implementations of a
few callbacks used by the Indirect Addressing pass and needs code to
handle frame indices.

At the moment R600 only supports array sizes of 16 dwords or less.
Register packing of vector types is currently disabled, which means that a
vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order
to correctly pack registers in all cases, we will need to implement an
analysis pass for R600 that determines the correct vector width for each
array.

v2:
  - Add support for i8 zext load from stack.
  - Coding style fixes

v3:
  - Don't reserve registers for indirect addressing when it isn't
    being used.
  - Fix bug caused by LLVM limiting the number of SubRegIndex
    declarations.

v4:
  - Fix 64-bit defines

llvm-svn: 174525
2013-02-06 17:32:29 +00:00
Tim Northover
a6ee94525f Implement external weak (ELF) symbols on AArch64
Weakly defined symbols should evaluate to 0 if they're undefined at
link-time. This is impossible to do with the usual address generation
patterns, so we should use a literal pool entry to materlialise the
address.

llvm-svn: 174518
2013-02-06 16:43:33 +00:00
Eli Bendersky
31f7dcd2e4 Add some comments to new frame entries
llvm-svn: 174515
2013-02-06 16:20:31 +00:00
Tim Northover
4daffb618d Add AArch64 CRC32 instructions
These instructions are a late addition to the architecture, and may
yet end up behind an optional attribute, but for now they're available
at all times.

llvm-svn: 174496
2013-02-06 09:13:13 +00:00
Tim Northover
45bdd458aa Add icache prefetch operations to AArch64
This adds hints to the various "prfm" instructions so that they can
affect the instruction cache as well as the data cache.

llvm-svn: 174495
2013-02-06 09:04:56 +00:00
Bill Wendling
2da9899378 Initial submission for the attribute group feature.
Attribute groups are of the form:

  #0 = attributes { noinline "no-sse" "cpu"="cortex-a8" alignstack=4 }

Target-dependent attributes are represented as strings. Attributes can have
optional values associated with them. E.g., the "cpu" attribute has the value
"cortex-a8".

Target-independent attributes are listed as enums inside the attribute classes.

Multiple attribute groups can be referenced by the same object. In that case,
the attributes are merged together.

llvm-svn: 174493
2013-02-06 06:52:58 +00:00
Craig Topper
4ba9d33da9 Remove extra blank line between closing curly brace and 'else'
llvm-svn: 174492
2013-02-06 06:50:38 +00:00
Craig Topper
d4a8a10013 Remove unused private field to suppress a build warning.
llvm-svn: 174491
2013-02-06 06:48:10 +00:00
Jim Grosbach
258f68e8a5 ARM: Use MCTargetAsmParser::validateTargetOperandClass().
Use the validateTargetOperandClass() hook to match literal '#0' operands in
InstAlias definitions. Previously this required per-instruction C++ munging of the
operand list, but not is handled as a natural part of the matcher. Much better.

No additional tests are required, as the pre-existing tests for these instructions
exercise the new behaviour as being functionally equivalent to the old.

llvm-svn: 174488
2013-02-06 06:00:11 +00:00
Eli Bendersky
935df72ee3 Failing builds because a private class member is not being used after
initialization is one of the reasons I consider -werror to be shoddy.

llvm-svn: 174485
2013-02-06 05:37:46 +00:00
Eli Bendersky
bd977c5c69 Add virtual desctructor to FrameEntry to avoid error on delete-non-virtual-dtor
llvm-svn: 174483
2013-02-06 03:08:02 +00:00
Evan Cheng
5bd979b50b Tweak check to avoid integer overflow (for insanely large alignments)
llvm-svn: 174482
2013-02-06 02:06:33 +00:00
Bill Wendling
f45bd45085 Add a 'StringRef' version of hasAttribute.
Fix the 'operator==' and 'hasAttributes' queries to take into account
target-dependent attributes.

llvm-svn: 174481
2013-02-06 01:33:42 +00:00
Bill Wendling
555fe288d9 Add methods to merge an AttrBuilder into another builder.
This is useful when parsing an object that references multiple attribute groups.

N.B. If both builders have alignments specified, then they should match!

llvm-svn: 174480
2013-02-06 01:16:00 +00:00
Manman Ren
6edff4edb0 Attempt to recover gdb bot after r174445.
Failure: undefined symbol 'Lline_table_start0'.
Root-cause: we use a symbol subtraction to calculate at_stmt_list, but
the line table entries are not dumped in the assembly.
Fix: use zero instead of a symbol subtraction for Compile Unit 0.

llvm-svn: 174479
2013-02-06 00:59:41 +00:00