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Author SHA1 Message Date
Craig Topper
e3c98d1dad [X86] Use EVT::getVectorVT instead of changeVectorElementType in reduceVMULWidth. 
Changing vector element type doesn't work for v6i32->v6i16 now
that v6i32 is an MVT and v6i16 is not.

I would like to fix this in changeVectorElementType, but you
need a LLVMContext to call getVectorVT which we can't get from
an MVT.

Fixes PR50709.
 2021-06-14 22:07:04 -07:00
Saleem Abdulrasool
a4fccf0a10 X86: pass swift_async context in R14 on Win64 
Pass swift_async context in a callee-saved register rather than as a
regular parameter.  This is similar to the Swift `self` and `error`
parameters.
 2021-06-14 11:02:21 -07:00
Eric Astor
d15098fdc8 [ms] [llvm-ml] When parsing MASM, "jmp short" instructions are case insensitive 
Handle "short" in a case-insensitive fashion in MASM.

Required to correctly parse z_Windows_NT-586_asm.asm from the OpenMP runtime.

Reviewed By: thakis

Differential Revision: https://reviews.llvm.org/D104195
 2021-06-13 18:36:00 -04:00
Eric Astor
3e051c60b8 Fix misspelled instruction in X86 assembly parser 
Did not correctly handle "jecxz short <address>".

Discovered while working on LLVM-ML; shows up in z_Windows_NT-586_asm.asm from the OpenMP runtime

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D104194
 2021-06-13 18:34:15 -04:00
Luo, Yuanke
426a9ac6ee [X86] Check immediate before get it. 
For CMP imm instruction, when the operand 1 is symbol address we should
check if it is immediate first. Here is the example code.
`CMP64mi32 $noreg, 8, killed renamable $rcx, @d, $noreg, @a, implicit-def
$eflags`
Many thanks to Craig, Topper for the test case to reproduce this issue.

Differential Revision: https://reviews.llvm.org/D104037
 2021-06-13 15:40:52 +08:00
Luo, Yuanke
c9854fe645 Revert "[X86] Check immediate before get it." 
This reverts commit 9eb2f723c24523194b833779d20b027bf89a4f55.
 2021-06-13 13:55:38 +08:00
Luo, Yuanke
4f7d0be5fe [X86] Check immediate before get it. 
For CMP imm instruction, when the operand 1 is symbol address we should
check if it is immediate first. Here is the example code.
`CMP64mi32 $noreg, 8, killed renamable $rcx, @d, $noreg, @a, implicit-def
$eflags`
Many thanks to Craig, Topper for the test case to reproduce this issue.

Differential Revision: https://reviews.llvm.org/D104037
 2021-06-13 09:08:40 +08:00
Craig Topper
e263936592 [X86] Add ISD::FREEZE and ISD::AssertAlign to the list of opcodes that don't guarantee upper 32 bits are zero. 
The freeze issue was reported here
https://llvm.discourse.group/t/bug-or-feature-freeze-instruction/3639

I don't have a test for AssertAlign. I just noticed it was missing
and assume it should be similar to the other two Asserts.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D104178
 2021-06-12 09:52:29 -07:00
Florian Hahn
f2662d35c8 Revert "[X86FixupLEAs] Transform the sequence LEA/SUB to SUB/SUB" 
This reverts commit 1b748faf2bae246e2fc77d88420df13c2e60f4df because it
breaks building the llvm-test-suite with -verify-machineinstrs on X86:
http://green.lab.llvm.org/green/job/test-suite-verify-machineinstrs-x86_64-O3/9585/

Running llc -verify-machineinstr on X86 crashes on the IR below:

    target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"

    %struct.widget = type { i32, i32, i32, i32, i32*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [16 x [16 x i16]], [6 x [32 x i32]], [16 x [16 x i32]], [4 x [12 x [4 x [4 x i32]]]], [16 x i32], i8**, i32*, i32***, i32**, i32, i32, i32, i32, %struct.baz*, %struct.wobble.1*, i32, i32, i32, i32, i32, i32, %struct.quux.2*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [3 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32***, i32***, i32****, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [3 x [2 x i32]], [3 x [2 x i32]], i32, i32, i64, i64, %struct.zot.3, %struct.zot.3, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
    %struct.baz = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.snork*, %struct.wombat.0*, %struct.wobble*, i32, i32*, i32*, i32*, i32, i32*, i32*, i32*, i32 (%struct.widget*, %struct.eggs*)*, i32, i32, i32, i32 }
    %struct.snork = type { %struct.spam*, %struct.zot, i32 (%struct.wombat*, %struct.widget*, %struct.snork*)* }
    %struct.spam = type { i32, i32, i32, i32, i8*, i32 }
    %struct.zot = type { i32, i32, i32, i32, i32, i8*, i32* }
    %struct.wombat = type { i32, i32, i32, i32, i32, i32, i32, i32, void (i32, i32, i32*, i32*)*, void (%struct.wombat*, %struct.widget*, %struct.zot*)* }
    %struct.wombat.0 = type { [4 x [11 x %struct.quux]], [2 x [9 x %struct.quux]], [2 x [10 x %struct.quux]], [2 x [6 x %struct.quux]], [4 x %struct.quux], [4 x %struct.quux], [3 x %struct.quux] }
    %struct.quux = type { i16, i8 }
    %struct.wobble = type { [2 x %struct.quux], [4 x %struct.quux], [3 x [4 x %struct.quux]], [10 x [4 x %struct.quux]], [10 x [15 x %struct.quux]], [10 x [15 x %struct.quux]], [10 x [5 x %struct.quux]], [10 x [5 x %struct.quux]], [10 x [15 x %struct.quux]], [10 x [15 x %struct.quux]] }
    %struct.eggs = type { [1000 x i8], [1000 x i8], [1000 x i8], i32, i32, i32, i32, i32, i32, i32, i32 }
    %struct.wobble.1 = type { i32, [2 x i32], i32, i32, %struct.wobble.1*, %struct.wobble.1*, i32, [2 x [4 x [4 x [2 x i32]]]], i32, i64, i64, i32, i32, [4 x i8], [4 x i8], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
    %struct.quux.2 = type { i32, i32, i32, i32, i32, %struct.quux.2* }
    %struct.zot.3 = type { i64, i16, i16, i16 }

    define void @blam(%struct.widget* %arg, i32 %arg1) local_unnamed_addr {
    bb:
      %tmp = load i32, i32* undef, align 4
      %tmp2 = sdiv i32 %tmp, 6
      %tmp3 = sdiv i32 undef, 6
      %tmp4 = load i32, i32* undef, align 4
      %tmp5 = icmp eq i32 %tmp4, 4
      %tmp6 = select i1 %tmp5, i32 %tmp3, i32 %tmp2
      %tmp7 = getelementptr inbounds [4 x [4 x i32]], [4 x [4 x i32]]* undef, i64 0, i64 0, i64 0
      %tmp8 = zext i16 undef to i32
      %tmp9 = zext i16 undef to i32
      %tmp10 = load i16, i16* undef, align 2
      %tmp11 = zext i16 %tmp10 to i32
      %tmp12 = zext i16 undef to i32
      %tmp13 = zext i16 undef to i32
      %tmp14 = zext i16 undef to i32
      %tmp15 = load i16, i16* undef, align 2
      %tmp16 = zext i16 %tmp15 to i32
      %tmp17 = zext i16 undef to i32
      %tmp18 = sub nsw i32 %tmp8, %tmp9
      %tmp19 = shl nsw i32 undef, 1
      %tmp20 = add nsw i32 %tmp19, %tmp18
      %tmp21 = sub nsw i32 %tmp11, %tmp12
      %tmp22 = shl nsw i32 undef, 1
      %tmp23 = add nsw i32 %tmp22, %tmp21
      %tmp24 = sub nsw i32 %tmp13, %tmp14
      %tmp25 = shl nsw i32 undef, 1
      %tmp26 = add nsw i32 %tmp25, %tmp24
      %tmp27 = sub nsw i32 %tmp16, %tmp17
      %tmp28 = shl nsw i32 undef, 1
      %tmp29 = add nsw i32 %tmp28, %tmp27
      %tmp30 = sub nsw i32 %tmp20, %tmp29
      %tmp31 = sub nsw i32 %tmp23, %tmp26
      %tmp32 = shl nsw i32 %tmp30, 1
      %tmp33 = add nsw i32 %tmp32, %tmp31
      store i32 %tmp33, i32* undef, align 4
      %tmp34 = mul nsw i32 %tmp31, -2
      %tmp35 = add nsw i32 %tmp34, %tmp30
      store i32 %tmp35, i32* undef, align 4
      %tmp36 = select i1 %tmp5, i32 undef, i32 undef
      br label %bb37

    bb37:                                             ; preds = %bb
      %tmp38 = load i32, i32* undef, align 4
      %tmp39 = ashr i32 %tmp38, %tmp6
      %tmp40 = load i32, i32* undef, align 4
      %tmp41 = sdiv i32 %tmp39, %tmp40
      store i32 %tmp41, i32* undef, align 4
      ret void
    }
 2021-06-12 11:41:38 +01:00
Florian Hahn
daff62b038 Revert "[X86FixupLEAs] Sub register usage of LEA dest should block LEA/SUB optimization" 
This reverts commit f35bcea1d4748889b8240defdf00cb7a71cbe070 because it
depends on 1b748faf2bae246e2fc77d88420df13c2e60f4df, which breaks
building the llvm-test-suite with -verify-machineinstrs on X86.

See 154adc0f135cff3f8a8861c335d2b88c8049d098 for more details.
 2021-06-12 11:40:47 +01:00
Guozhi Wei
0b1bb7b700 [X86FixupLEAs] Sub register usage of LEA dest should block LEA/SUB optimization 
In function searchALUInst, sub register usage of LEA dest should also block LEA/SUB optimization, otherwise the sub register usage gets an undefined value.

This patch fixes https://bugs.llvm.org/show_bug.cgi?id=50615.

Differential Revision: https://reviews.llvm.org/D103922
 2021-06-11 09:45:56 -07:00
Simon Pilgrim
165132af1b [ADT] Remove APInt/APSInt toString() std::string variants 
<string> is currently the highest impact header in a clang+llvm build:

https://commondatastorage.googleapis.com/chromium-browser-clang/llvm-include-analysis.html

One of the most common places this is being included is the APInt.h header, which needs it for an old toString() implementation that returns std::string - an inefficient method compared to the SmallString versions that it actually wraps.

This patch replaces these APInt/APSInt methods with a pair of llvm::toString() helpers inside StringExtras.h, adjusts users accordingly and removes the <string> from APInt.h - I was hoping that more of these users could be converted to use the SmallString methods, but it appears that most end up creating a std::string anyhow. I avoided trying to use the raw_ostream << operators as well as I didn't want to lose having the integer radix explicit in the code.

Differential Revision: https://reviews.llvm.org/D103888
 2021-06-11 13:19:15 +01:00
Bing1 Yu
c7250ce1db [X86] Support __tile_stream_loadd intrinsic for new AMX interface 
Adding support for __tile_stream_loadd intrinsic.

Reviewed By: LuoYuanke

Differential Revision: https://reviews.llvm.org/D103784
 2021-06-11 17:28:43 +08:00
Luo, Yuanke
83aebff64b [X86][NFC] Fix typo. 2021-06-10 22:49:11 +08:00
Craig Topper
c39f9ef639 [X86] Check destination element type before forming VTRUNCS/VTRUNCUS in combineTruncateWithSat. 
Fixes crash reported here https://reviews.llvm.org/D73607

Using a store to keep the trunc intact. Returning v16i24 would
cause the trunc to be optimized away in SelectionDAGBuilder.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D103940
 2021-06-09 07:08:17 -07:00
Simon Pilgrim
91a6df2ba4 [X86][SLM] Adjust XMM non-PMULLD throughput costs to half rate. 
Match what's reported in the costs table, Agner's tables and the Intel AOM
 2021-06-09 13:51:40 +01:00
Nick Desaulniers
42052632ff reland [IR] make -stack-alignment= into a module attr 
Relands commit 433c8d950cb3a1fa0977355ce0367e8c763a3f13 with fixes for
MIPS.

Similar to D102742, specifying the stack alignment via CodegenOpts means
that this flag gets dropped during LTO, unless the command line is
re-specified as a plugin opt. Instead, encode this information as a
module level attribute so that we don't have to expose this llvm
internal flag when linking the Linux kernel with LTO.

Looks like external dependencies might need a fix:
* https://github.com/llvm-hs/llvm-hs/issues/345
* https://github.com/halide/Halide/issues/6079

Link: https://github.com/ClangBuiltLinux/linux/issues/1377

Reviewed By: tejohnson

Differential Revision: https://reviews.llvm.org/D103048
 2021-06-08 10:59:46 -07:00
Nick Desaulniers
579f298a64 Revert "[IR] make -stack-alignment= into a module attr" 
This reverts commit 433c8d950cb3a1fa0977355ce0367e8c763a3f13.

Breaks the MIPS build.
 2021-06-08 08:55:50 -07:00
Nick Desaulniers
5c936095e3 [IR] make -stack-alignment= into a module attr 
Similar to D102742, specifying the stack alignment via CodegenOpts means
that this flag gets dropped during LTO, unless the command line is
re-specified as a plugin opt. Instead, encode this information as a
module level attribute so that we don't have to expose this llvm
internal flag when linking the Linux kernel with LTO.

Looks like external dependencies might need a fix:
* https://github.com/llvm-hs/llvm-hs/issues/345
* https://github.com/halide/Halide/issues/6079

Link: https://github.com/ClangBuiltLinux/linux/issues/1377

Reviewed By: tejohnson

Differential Revision: https://reviews.llvm.org/D103048
 2021-06-08 08:31:04 -07:00
Simon Pilgrim
b21f333bb4 [CostModel][X86] Improve AVX1/AVX2 truncation costs 
Based off the worse case numbers generated by D103695, we were overestimating the cost of a number of vector truncations:

AVX2: v2i32->v2i8, v2i64->v2i16 + v4i64->v4i32
AVX1: v2i32->v2i8, v4i64->v4i16 + v16i16->v16i8

Once we have a working set of conversion costs, the intention is to cleanup the tables and use legalized types a lot more to reduce the number of entries we currently have.
 2021-06-08 10:41:03 +01:00
Harald van Dijk
9e8b1c8ad9 [X32] Add Triple::isX32(), use it. 
So far, support for x86_64-linux-gnux32 has been handled by explicit
comparisons of Triple.getEnvironment() to GNUX32. This worked as long as
x86_64-linux-gnux32 was the only X32 environment to worry about, but we
now have x86_64-linux-muslx32 as well. To support this, this change adds
an isX32() function and uses it. It replaces all checks for GNUX32 or
MuslX32 by isX32(), except for the following:

- Triple::isGNUEnvironment() and Triple::isMusl() are supposed to treat
  GNUX32 and MuslX32 differently.
- computeTargetTriple() needs to be able to transform triples to add or
  remove X32 from the environment and needs to map GNU to GNUX32, and
  Musl to MuslX32.
- getMultiarchTriple() completely lacks any Musl support and retains the
  explicit check for GNUX32 as it can only return x86_64-linux-gnux32.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D103777
 2021-06-07 20:48:39 +01:00
Simon Pilgrim
779c968967 [CostModel][X86] Add 512-bit bswap costs 2021-06-06 22:36:34 +01:00
Simon Pilgrim
3d02a9f278 [CostModel][X86] Improve AVX512 FDIV costs 
Add missing v16f32/v8f64 costs and adjust other costs as well based off the SkylakeServer model
 2021-06-06 21:41:05 +01:00
Simon Pilgrim
0e6ebc4153 [X86][SSE] LowerFP_TO_INT - remove dead code. NFCI. 
Non-Strict v2f32->v2i64 cases have already early-returned to be handled by legalization.
 2021-06-06 20:04:15 +01:00
Simon Pilgrim
2cad20b386 [X86][SSE] combineVectorTruncation - simplify PSHUFB-is-better logic. NFCI. 
OutSVT is guaranteed to be i8/i16 and we accept any InSVT that isn't i64
 2021-06-06 20:04:14 +01:00
Simon Pilgrim
ee630c4d10 X86MachObjectWriter.cpp - silence null deference warnings. NFCI. 
The MCSymbol data should always be present for non-absolute sections so assert that it is to silence static analysis warnings.
 2021-06-06 15:33:47 +01:00
Nikita Popov
6fa17c5cd4 [TargetLowering] Use IRBuilderBase instead of IRBuilder<> (NFC) 
Don't require a specific kind of IRBuilder for TargetLowering hooks.
This allows us to drop the IRBuilder.h include from TargetLowering.h.

Differential Revision: https://reviews.llvm.org/D103759
 2021-06-06 16:29:50 +02:00
Simon Pilgrim
1271ac390e X86Operand.h - fix uninitialized variable warnings in constructor. NFCI. 2021-06-06 15:25:03 +01:00
Nikita Popov
a84c0ba160 [CodeGen] Add missing includes (NFC) 
These currently rely on the IRBuilder.h include in TargetLowering.h.
Make them explicit.
 2021-06-06 15:48:27 +02:00
Fangrui Song
0d92547dcb Fix some -Wunused-but-set-variable in -DLLVM_ENABLE_ASSERTIONS=off build 2021-06-04 23:34:43 -07:00
Roman Lebedev
55213cd08b [X86] AMD Zen 3: double the LoopMicroOpBufferSize 
While the IndVars issue (PR50384) has been resolved,
and the compile performance improved, a new blocker emerged,
the codegen machine instruction scheduling is also quadratic.
So we still can't really specify the right value here.

Filed PR50584.
 2021-06-05 01:23:58 +03:00
Rong Xu
559805b594 [SampleFDO] New hierarchical discriminator for FS SampleFDO (llvm-profdata part) 
This patch was split from https://reviews.llvm.org/D102246
[SampleFDO] New hierarchical discriminator for Flow Sensitive SampleFDO
This is for llvm-profdata part of change. It sets the bit masks for the
profile reader in llvm-profdata. Also add an internal option
"-fs-discriminator-pass" for show and merge command to process the profile
offline.

This patch also moved setDiscriminatorMaskedBitFrom() to
SampleProfileReader::create() to simplify the interface.

Differential Revision: https://reviews.llvm.org/D103550
 2021-06-04 11:22:06 -07:00
Fangrui Song
dfa955b8df [MC] Delete unneeded MCAsmParser &Parser 2021-06-02 16:10:18 -07:00
Fangrui Song
5ddfda0ee0 [MC] Change "unexpected tokens" to "expected newline" and remove unneeded "in .xxx directive" 2021-06-02 16:08:05 -07:00
Simon Pilgrim
7b5702378b [X86][SSE] combineScalarToVector - only reuse broadcasts for scalar_to_vector if the source operands scalar types match 
We were hitting an issue when the scalar_to_vector source was being implicitly truncated (in this case to i8 to vXi1) but we were also using the i8 source in a broadcast to a vXi8 value.

Fixes PR50374
 2021-06-02 22:05:40 +01:00
Min-Yih Hsu
fc07b73b83 [CodeGen][NFC] Remove unused virtual function 
`TargetFrameLowering::emitCalleeSavedFrameMoves` with 4 arguments is not
used anywhere in CodeGen. Thus it shouldn't be exposed as a virtual
function. NFC.

Differential Revision: https://reviews.llvm.org/D103328
 2021-06-02 13:11:12 -07:00
Rong Xu
f505b894a2 [SampleFDO] New hierarchical discriminator for FS SampleFDO (ProfileData part) 
This patch was split from https://reviews.llvm.org/D102246
[SampleFDO] New hierarchical discriminator for Flow Sensitive SampleFDO
This is mainly for ProfileData part of change. It will load
FS Profile when such profile is detected. For an extbinary format profile,
create_llvm_prof tool will add a flag to profile summary section.
For other format profiles, the users need to use an internal option
(-profile-isfs) to tell the compiler that the profile uses FS discriminators.

This patch also simplified the bit API used by FS discriminators.

Differential Revision: https://reviews.llvm.org/D103041
 2021-06-02 10:32:52 -07:00
Michael Benfield
f8d5955717 [various] Remove or use variables which are unused but set. 
This is in preparation for the -Wunused-but-set-variable warning.

Differential Revision: https://reviews.llvm.org/D102942
 2021-06-01 15:38:48 -07:00
Daniel Sanders
71a22fb7f8 [globalisel][legalizer] Separate the deprecated LegalizerInfo from the current one 
It's still in use in a few places so we can't delete it yet but there's not
many at this point.

Differential Revision: https://reviews.llvm.org/D103352
 2021-06-01 13:23:48 -07:00
Guozhi Wei
b2dfe60e88 [X86FixupLEAs] Transform the sequence LEA/SUB to SUB/SUB 
This patch transforms the sequence

    lea (reg1, reg2), reg3
    sub reg3, reg4

to two sub instructions

    sub reg1, reg4
    sub reg2, reg4

Similar optimization can also be applied to LEA/ADD sequence.
The modifications to TwoAddressInstructionPass is to ensure the operands of ADD
instruction has expected order (the dest register of LEA should be src register of ADD).

Differential Revision: https://reviews.llvm.org/D101970
 2021-06-01 10:31:30 -07:00
Roman Lebedev
0573b00888 [X86] AMD Zen 3 has fast variable per-lane shuffles 
... but lane-crossing shuffles are slow.
 2021-06-01 10:46:05 +03:00
Roman Lebedev
19a9e819da [X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants 
Currently, X86 backend only has a global one-size-fits-all `FeatureFastVariableShuffle` feature,
which controls profitability of both the cross-lane and per-lane variable shuffles.
I guess, this has been fine so far.

But at least on AMD Zen 3, while per-line variable shuffles (e.g. `VPSHUFB`)
are as fast as as shuffles with fixed/immediate mask,
while lane-crossing shuffles, e.g. `VPERMPS` is performing worse.

So to get the benefits of variable-mask shuffles, but not the drawbacks of lane-crossing shuffles,
as suggested by @RKSimon, split the feature flag into two.

Differential Revision: https://reviews.llvm.org/D103274
 2021-06-01 10:39:36 +03:00
Tim Northover
859ff3505c SwiftTailCC: teach verifier musttail rules applicable to this CC. 
SwiftTailCC has a different set of requirements than the C calling convention
for a tail call. The exact argument sequence doesn't have to match, but fewer
ABI-affecting attributes are allowed.

Also make sure the musttail diagnostic triggers if a musttail call isn't
actually a tail call.
 2021-05-28 11:12:00 +01:00
Simon Pilgrim
0c78aae183 [CostModel][X86] Improve accuracy of sext/zext to 256-bit vector costs on AVX1 targets 
Determined from llvm-mca analysis (btver2 vs bdver2 vs sandybridge), the split+extends+concat sequence on AVX1 capable targets are cheaper than the #ops that the cost was previously based on.
 2021-05-27 18:17:50 +01:00
Craig Topper
3180a39f2d [X86] Fold (shift undef, X)->0 for vector shifts by immediate. 
We could previously do this by accident through the later
call to getTargetConstantBitsFromNode I think, but that only worked
if N0 had a single use. This patch makes it explicit for undef and
doesn't have a use count check.

I think this is needed to move the (shl X, 1)->(add X, X)
fold to isel for PR50468. We need to be sure X won't be IMPLICIT_DEF
which might prevent the same vreg from being used for both operands.

Differential Revision: https://reviews.llvm.org/D103192
 2021-05-27 09:31:47 -07:00
Simon Pilgrim
154058d3b3 [CostModel][X86] AVX512 truncation ops are slower than cost models indicate. 
The SkylakeServer model (and later IceLake/TigerLake targets according to Agner) have the PMOV truncations as uops=2, rthroughput=2 instructions.

Noticed while trying to reduce the diffs between cost tables and llvm-mca analysis.
 2021-05-27 16:07:42 +01:00
Luo, Yuanke
47e83818b4 [X86][AMX] Fix a bug on tile config. 
The previous code detect if a MBB is bottom block to determine if it is
a backedge of a loop. We should check latch block instead of bottom
block and we should check the header and the bottom block are in the
same loop.

Differential Revision: https://reviews.llvm.org/D103145
 2021-05-26 21:57:49 +08:00
Simon Pilgrim
6128b86b1d [X86][SLM] Fix vector PSHUFB + variable shift resource/throughputs 
Match whats documented in the Intel AOM (+Agner) - PSHUFB xmm is really slow, and mmx/xmm vector shifts are half rate.

Noticed while working to get the cost tables to more closely match llvm-mca analysis, in this case for shifts and truncations.
 2021-05-26 11:14:21 +01:00
Simon Pilgrim
f18fae2383 [X86][Atom] Fix vector variable shift resource/throughputs 
Match whats documented in the Intel AOM - the non-immediate variants of the PSLL*/PSRA*/PSRL* shift instructions requires BOTH ports - this was being incorrectly modelled as EITHER port.

Now that we can use in-order models in llvm-mca, the atom model is a good "worst case scenario" analysis for x86.
 2021-05-26 10:30:59 +01:00
Roman Lebedev
395eb3f2e5 [NFC][X86] clang-format X86TTIImpl::getInterleavedMemoryOpCostAVX2() 
I plan to make changes to it, and undoing formatting each time is not going to be fun.
 2021-05-26 12:27:47 +03:00