Chris Lattner
ed4920842f
Add XLForm_1_ext template, patch by Nicolas Geoffray.
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llvm-svn: 34573
2007-02-25 05:07:49 +00:00
Chris Lattner
82157643ed
fix another sradi encoding bug. This fixes Olden/health with the ppc64 jit.
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llvm-svn: 32291
2006-12-06 21:35:10 +00:00
Chris Lattner
6d74c6ebec
fix the jit encoding of sradi, simplify the MDForm1 description.
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llvm-svn: 32285
2006-12-06 20:02:54 +00:00
Chris Lattner
f50d87eb50
Rewrite the branch selector to be correct in the face of large functions.
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The algorithm it used before wasn't 100% correct, we now use an iterative
expansion model. This fixes assembler errors when compiling 403.gcc with
tail merging enabled.
Change the way the branch selector works overall: Now, the isel generates
PPC::BCC instructions (as it used to) directly, and these BCC instructions
are emitted to the output or jitted directly if branches don't need
expansion. Only if branches need expansion are instructions rewritten
and created. This should make branch select faster, and eliminates the
Bxx instructions from the .td file.
llvm-svn: 31837
2006-11-18 00:32:03 +00:00
Chris Lattner
a5439b7913
add encoding for BCC, after finally wrestling strange ppc/tblgen endianness
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issues to the ground.
llvm-svn: 31836
2006-11-17 23:53:28 +00:00
Chris Lattner
bd95b9d4ae
Stop using isTwoAddress, switching to operand constraints instead.
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Tell the codegen emitter that specific operands are not to be encoded, fixing
JIT regressions w.r.t. pre-inc loads and stores (e.g. lwzu, which we generate
even when general preinc loads are not enabled).
llvm-svn: 31770
2006-11-15 23:24:18 +00:00
Chris Lattner
1aaa5f904c
implement preinc support for r+i loads on ppc64
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llvm-svn: 31654
2006-11-10 23:58:45 +00:00
Chris Lattner
5e975945a5
dform 8/9 are identical to dform 1
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llvm-svn: 31637
2006-11-10 17:51:02 +00:00
Chris Lattner
bed20e1a25
fix encoding of BLR
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llvm-svn: 31485
2006-11-07 01:51:50 +00:00
Chris Lattner
a193c9c977
encode BLR predicate info for the JIT
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llvm-svn: 31450
2006-11-04 05:42:48 +00:00
Chris Lattner
5c489bce2c
Another fix in the rotate encodings, needed when the first two operands are not
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the same.
llvm-svn: 29136
2006-07-13 21:52:41 +00:00
Chris Lattner
726ca018c0
Fix encoding of rotates, such as rldicl
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llvm-svn: 29128
2006-07-12 22:08:13 +00:00
Chris Lattner
86c7ca4fd4
Add a pattern for i64 sra. Print 8-byte units with a space between the .quad
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and the data
llvm-svn: 28934
2006-06-27 20:07:26 +00:00
Chris Lattner
75e6449a0f
Rename OR4 -> OR. Move some PPC64-specific stuff to the 64-bit file
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llvm-svn: 28889
2006-06-20 23:18:58 +00:00
Chris Lattner
2e1d3158f1
remove unused flag
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llvm-svn: 28888
2006-06-20 23:15:07 +00:00
Chris Lattner
bfbee64ecf
Add PowerPC intrinsics to support dcbz[l]
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llvm-svn: 28696
2006-06-06 21:29:23 +00:00
Chris Lattner
7f13e50435
Add all of the data stream intrinsics and instructions. woo
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llvm-svn: 27442
2006-04-05 22:27:14 +00:00
Chris Lattner
66c3b75644
Add m[tf]vscr instructions.
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llvm-svn: 27421
2006-04-05 00:03:57 +00:00
Chris Lattner
4b0fc38fe7
Fix the JIT encoding of VSEL
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llvm-svn: 27160
2006-03-27 03:34:17 +00:00
Chris Lattner
b5efa3e0f5
Fix the JIT encoding of VSPLTI*
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llvm-svn: 27159
2006-03-27 03:28:57 +00:00
Chris Lattner
f0c36b99e6
Add all of the altivec comparison instructions. Add patterns for the
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non-predicate altivec compare intrinsics.
llvm-svn: 27143
2006-03-26 04:57:17 +00:00
Chris Lattner
d33ef7a1bc
implement the vsldoi intrinsic.
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llvm-svn: 27139
2006-03-26 00:41:48 +00:00
Chris Lattner
2e606dc60f
Fix the JIT encoding of the VAForm_1 instructions, including vmaddfp
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llvm-svn: 26935
2006-03-22 01:44:36 +00:00
Chris Lattner
ba10d4e4ab
Mark instructions that are cracked by the PPC970 decoder as such.
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llvm-svn: 26720
2006-03-13 05:15:10 +00:00
Chris Lattner
a278639f29
Several big changes:
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1. Use flags on the instructions in the .td file to indicate the PPC970 unit
type instead of a table in the .cpp file. Much cleaner.
2. Change the hazard recognizer to build d-groups according to the actual
algorithm used, not my flawed understanding of it.
3. Model "must be in the first slot" and "must be the only instr in a group"
accurately.
llvm-svn: 26719
2006-03-12 09:13:49 +00:00
Chris Lattner
20d4194a0d
PHI and INLINEASM are now built-in instructions provided by Target.td
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llvm-svn: 25674
2006-01-27 01:46:15 +00:00
Nate Begeman
a114534620
Pattern-match return. Includes gross hack!
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llvm-svn: 24874
2005-12-20 00:26:01 +00:00
Nate Begeman
09855eafd1
Add support for fmul node of type v4f32.
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void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = mul <4 x float> %tmp1, %tmp1
store <4 x float> %tmp2, <4 x float> *%a
ret void
}
Is selected to:
_foo:
li r2, 0
lvx v0, r2, r3
vxor v1, v1, v1
vmaddfp v0, v0, v0, v1
stvx v0, r2, r3
blr
llvm-svn: 24701
2005-12-14 00:34:09 +00:00
Nate Begeman
5c6a84b5fc
Add support patterns to many load and store instructions which will
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hopefully use patterns in the near future.
llvm-svn: 24651
2005-12-09 23:54:18 +00:00
Chris Lattner
b62b05bde6
Define BR in the .td file now that Evan made tblgen smarter.
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llvm-svn: 24589
2005-12-04 18:42:54 +00:00
Nate Begeman
ebafe9c6d8
Represent the encoding of the SPR instructions as they actually are, so
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that we can use the correct SPR numbers in the InstrInfo.td file. This is
necessary to support VRsave.
llvm-svn: 24521
2005-11-29 22:42:50 +00:00
Nate Begeman
16a1c53abc
Add the remainder of the AltiVec 4 x float instructions. Further
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enhancements will be necessary to teach the code generator that since
there is no fmul, it will have to do vmaddfp, adding +0.0.
llvm-svn: 24516
2005-11-29 08:04:45 +00:00
Nate Begeman
84cac055ad
Small tweaks noticed while on the plane.
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llvm-svn: 24492
2005-11-26 22:39:34 +00:00
Nate Begeman
687456dd7a
Some first bits of AltiVec stuff: Instruction Formats, Encodings, and
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Registers. Apologies to Jim if the scheduling info so far isn't accurate.
There's a few more things like VRsave support that need to be finished up
in my local tree before I can commit code that Does The Right Thing for
turning 4 x float into the various altivec packed float instructions.
llvm-svn: 24489
2005-11-23 05:29:52 +00:00
Chris Lattner
a701ef16fc
Allow pseudos to have patterns, no functionality change
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llvm-svn: 23988
2005-10-25 20:58:43 +00:00
Jim Laskey
514a74d946
Added InstrSchedClass to each of the PowerPC Instructions.
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Note that when adding new instructions that you should refer to the table at the
bottom of PPCSchedule.td.
llvm-svn: 23830
2005-10-19 19:51:16 +00:00
Nate Begeman
83f0f34140
Write patterns for the various shl and srl patterns that don't involve
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doing something clever.
llvm-svn: 23824
2005-10-19 18:42:01 +00:00
Chris Lattner
11127fcf98
Rename PowerPC*.td -> PPC*.td
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llvm-svn: 23740
2005-10-14 23:40:39 +00:00