1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 11:13:28 +01:00
Commit Graph

157413 Commits

Author SHA1 Message Date
Sanjoy Das
4c91f785c4 [SCEV] A different fix for PR33494
Summary:
I don't think rL309080 is the right fix for PR33494 -- caching ExitLimit only
hides the problem[0].  The real issue is that because of how we forget SCEV
expressions ScalarEvolution::getBackedgeTakenInfo, in the test case for PR33494
computing the backedge for any loop invalidates the trip count for every other
loop.  This effectively makes the SCEV cache useless.

I've instead made the SCEV expression invalidation in
ScalarEvolution::getBackedgeTakenInfo less aggressive to fix this issue.

[0]: One way to think about this is that rL309080 essentially augmented the
backedge-taken-count cache with another equivalent exit-limit cache.  The bug
went away because we were explicitly not clearing the exit-limit cache in
getBackedgeTakenInfo.  But instead of doing all of that, we can just avoid
clearing the backedge-taken-count cache.

Reviewers: mkazantsev, mzolotukhin

Subscribers: mcrosier, llvm-commits

Differential Revision: https://reviews.llvm.org/D39361

llvm-svn: 319678
2017-12-04 19:22:00 +00:00
Sanjoy Das
7d237893d7 [BypassSlowDivision] Improve our handling of divisions by constants
(This reapplies r314253.  r314253 was reverted on r314482 because of a
correctness regression on P100, but that regression was identified to be
something else.)

Summary:
Don't bail out on constant divisors for divisions that can be narrowed without
introducing control flow .  This gives us a 32 bit multiply instead of an
emulated 64 bit multiply in the generated PTX assembly.

Reviewers: jlebar

Subscribers: jholewinski, mcrosier, llvm-commits

Differential Revision: https://reviews.llvm.org/D38265

llvm-svn: 319677
2017-12-04 19:21:58 +00:00
Matthias Braun
17255ac179 MachineVerifier: undef phi arg doesn't need to be live-out from predecessor
Differential Revision: https://reviews.llvm.org/D40756

llvm-svn: 319674
2017-12-04 18:57:48 +00:00
Francis Visoiu Mistrih
30264d4391 [CodeGen] Unify MBB reference format in both MIR and debug output
As part of the unification of the debug format and the MIR format, print
MBB references as '%bb.5'.

The MIR printer prints the IR name of a MBB only for block definitions.

* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g'
* find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g'
* grep -nr 'BB#' and fix

Differential Revision: https://reviews.llvm.org/D40422

llvm-svn: 319665
2017-12-04 17:18:51 +00:00
Pablo Barrio
8611fff6da Fix function pointer tail calls in armv8-M.base
Summary:
The compiler fails with the following error message:

fatal error: error in backend: ran out of registers during
register allocation

Tail call optimization for Armv8-M.base fails to meet all the required
constraints when handling calls to function pointers where the
arguments take up r0-r3. This is because the pointer to the
function to be called can only be stored in r0-r3, but these are
all occupied by arguments. This patch makes sure that tail call
optimization does not try to handle this type of calls.

Reviewers: chill, MatzeB, olista01, rengolin, efriedma

Reviewed By: olista01, efriedma

Subscribers: efriedma, aemerson, javed.absar, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D40706

llvm-svn: 319664
2017-12-04 16:55:49 +00:00
Pavel Labath
1431200847 Revert "[cmake] Enable zlib support on windows"
This reverts commit r319533 as it broke llvm-config --system-libs output
and everything that depends on it (which is mostly out of tree or
downstream folks, but includes a couple of llvm buildbots as well).

I think I have a fix for this in D40779, but I want someone to look
review it first. In the mean time, I am reverting this change, as it
seems to break a lot of people.

llvm-svn: 319663
2017-12-04 16:46:20 +00:00
Sam Kolton
9d2dd75cdb [AMDGPU] SDWA: add support for PRESERVE into SDWA peephole.
Summary:

Reviewers: arsenm, vpykhtin, rampitec

Subscribers: kzhuravl, wdng, nhaehnle, mgorny, yaxunl, dstuttard, tpr, t-tye

Differential Revision: https://reviews.llvm.org/D37817

llvm-svn: 319662
2017-12-04 16:22:32 +00:00
Sam Parker
334d9927ad [ARM] CodeGen test
Add another and + load DAG combine test.

llvm-svn: 319660
2017-12-04 15:14:59 +00:00
Anna Thomas
d774acff85 [Loop Predication] Teach LP about reverse loops
Summary:
Currently, we only support predication for forward loops with step
of 1.  This patch enables loop predication for reverse or
countdownLoops, which satisfy the following conditions:
   1. The step of the IV is -1.
   2. The loop has a singe latch as B(X) = X <pred>
latchLimit with pred as s> or u>
   3. The IV of the guard is the decrement
IV of the latch condition (Guard is: G(X) = X-1 u< guardLimit).

This patch was downstream for a while and is the last series of patches
that's from our LP implementation downstream.

Reviewers: apilipenko, mkazantsev, sanjoy

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D40353

llvm-svn: 319659
2017-12-04 15:11:48 +00:00
Jonas Hahnfeld
ea59814b3d [NVPTX] Assign valid global names
PTX requires that identifiers consist only of [a-zA-Z0-9_$]. The
existing pass already ensured this for globals and this patch adds
the cleanup for functions with local linkage.

However, there was a different problem in the case of collisions
of the adjusted name: The ValueSymbolTable then automatically
appended ".N" with increasing Ns to get a unique name while helping
the ABI demangling. Special case this behavior to omit the dots and
append N directly. This will always give us legal names according
to the PTX requirements.

Differential Revision: https://reviews.llvm.org/D40573

llvm-svn: 319657
2017-12-04 14:19:33 +00:00
Jonas Devlieghere
5b49122bce [NFC][lit] Use proper semantic versioning names for variables
The variable named `minor` was actually pointing to the patch part of
the version. While I was changing this I also made the check for Apple
clang more robust by checking both patch and minor rather than just
minor.

llvm-svn: 319656
2017-12-04 14:01:34 +00:00
Oliver Stannard
3a098791a4 Revert r319649 - [Asm, ARM] Add fallback diag for multiple invalid operands
This is causing a failure in the llvm-clang-x86_64-expensive-checks-win
buildbot, and I can't reproduce it locally, so reverting until I can work out
what is wrong.

llvm-svn: 319654
2017-12-04 13:42:22 +00:00
Sam McCall
409fc25f58 Revert "[ValueTracking] Pass only a single lambda to computeKnownBitsFromShiftOperator by using KnownBits struct instead of separate APInts. NFCI"
This reverts commit r319624, which seems to cause a miscompile (breaks the
multistage PPC buildbots)

llvm-svn: 319652
2017-12-04 12:51:49 +00:00
Tim Corringham
5f5cc0949f AMDGPU: fix missing s_waitcnt
Summary:
The pass that inserts s_waitcnt instructions where needed propagated
info used to track dependencies for each block by iterating over the
predecessor blocks. The iteration was terminated when a predecessor
that had not yet been processed was encountered. Any info in blocks
later in the list was therefore not processed, leading to the
possiblility of a required s_waitcnt not being inserted.

The fix is simply to change the "break" to "continue" for the
relevant loops, so that all visited blocks are processed. This
is likely what was intended when the code was written.

There is no test case provided for this fix because:
1) the only example that reproduces this is large and resistant to
being reduced
2) the change is trivial

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye

Differential Revision: https://reviews.llvm.org/D40544

llvm-svn: 319651
2017-12-04 12:30:49 +00:00
Oliver Stannard
34dd7b5bff [Asm, ARM] Add fallback diag for multiple invalid operands
This adds a "invalid operands for instruction" diagnostic for
instructions where there is an instruction encoding with the correct
mnemonic and which is available for this target, but where multiple
operands do not match those which were provided. This makes it clear
that there is some combination of operands that is valid for the current
target, which the default diagnostic of "invalid instruction" does not.

Since this is a very general error, we only emit it if we don't have a
more specific error.

Differential revision: https://reviews.llvm.org/D36747

llvm-svn: 319649
2017-12-04 12:02:32 +00:00
Jonas Paulsson
e58a4a3cf9 [TwoAddressInstructionPass] Bugfix in handling of sunk instructions.
An instruction returned by TII->convertToThreeAddress() may contain a %noreg
(undef) operand, which is not expected by tryInstructionTransform(). So if
this MI is sunk to a lower point in MBB, it must be skipped when later
encountered.

A new set SunkInstrs is used for this purpose.

Note: there is no test supplied here, as this was triggered on SystemZ while
working on a review of instruction flags. A test case for this bugfix will be
included in the upcoming SystemZ commit.

Review: Quentin Colombet
https://reviews.llvm.org/D40711

llvm-svn: 319646
2017-12-04 10:03:14 +00:00
Sam Parker
a32c9d6758 [DAGCombine] Remove isAndLoadExtLoad arguments
Both LoadedVT and NarrowLoad are passed as references and neither
of them are used by any of its callers.

Differential Revision: https://reviews.llvm.org/D40713

llvm-svn: 319645
2017-12-04 09:48:26 +00:00
Martin Storsjo
fb960f72cb [AArch64] Allow using emulated tls on platforms other than ELF
This matches how it is done on X86.

This allows using emulated tls on windows; in MinGW environments,
native tls isn't supported at the moment.

Set the right Data*bitsDirective for windows to match the existing
tests for other platforms. Make parts of the existing tests a regex,
to allow matching .section .rdata for windows, to avoid having to
duplicate the rest of the tests for windows.

Differential Revision: https://reviews.llvm.org/D40770

llvm-svn: 319644
2017-12-04 09:09:04 +00:00
Martin Storsjo
4d715b956b [ARM] Allow using emulated tls on platforms other than ELF
This matches how it is done on X86.

This allows using emulated tls on windows; in MinGW environments,
native tls isn't supported at the moment.

Differential Revision: https://reviews.llvm.org/D40769

llvm-svn: 319643
2017-12-04 09:08:55 +00:00
Craig Topper
817e51fda5 [X86] Allow VPMAXUQ/VPMAXSQ/VPMINUQ/VPMINSQ to be used with 128/256 bit vectors when AVX512 is enabled.
These instructions can be used by widening to 512-bits and extracting back to 128/256. We do similar to several other instructions already.

llvm-svn: 319641
2017-12-04 07:21:01 +00:00
Craig Topper
501addbf5d [X86] Don't turn UINT_TO_FP into SINT_TO_FP during lowering.
We already do this as a DAG combine. The version during lowering can only trigger if known bits changes something that improves known bits analysis. But this means we should be improving known bits analysis to work on the unlowered form instead.

llvm-svn: 319640
2017-12-04 05:38:44 +00:00
Craig Topper
1a26f5693b [SelectionDAG] Teach computeKnownBits some improvements to ISD::SRL with a non-splat constant shift amount.
If we have a non-splat constant shift amount, the minimum shift amount can be used to infer the number of zero upper bits of the result. There's probably a lot more that we can do here, but this
fixes a case where I wanted to infer the sign bit as zero when all the shift amounts are non-zero.

llvm-svn: 319639
2017-12-04 05:38:42 +00:00
Simon Pilgrim
4ff02a612d [X86][AVX512] Tag PH2PS/PS2PH conversion instructions scheduler classes
llvm-svn: 319637
2017-12-03 21:43:54 +00:00
Simon Pilgrim
2e56ab4844 [X86][AVX512] Tag packed F2I/I2F/F2F conversion instructions scheduler class
llvm-svn: 319636
2017-12-03 21:16:12 +00:00
Simon Pilgrim
3dc18e28c7 [X86][AVX512] Regenerate schedule tests.
llvm-svn: 319635
2017-12-03 21:07:36 +00:00
Simon Pilgrim
1964f1291a [X86][SSE] Remove unused IIC_SSE_CVT_PI2PS_RR/IIC_SSE_CVT_PI2PS_RM itineraries
llvm-svn: 319634
2017-12-03 20:57:04 +00:00
Yaxun Liu
7b8d4b7949 CodeGen: Fix SelectionDAGISel::LowerArguments for sret addr space
SelectionDAGISel::LowerArguments assumes sret addr space is 0, which is
not true for amdgcn---amdgiz target.

This patch fixes that.

Differential Revision: https://reviews.llvm.org/D40255

llvm-svn: 319630
2017-12-03 03:31:45 +00:00
Craig Topper
8c07f8a487 [SelectionDAG] Use the inlined APInt shift methods since we've already bounds checked the shift.
The version that takes APInt is out of line. The 'unsigned' version optimizes for the common case of single word APInts.

llvm-svn: 319628
2017-12-03 03:07:09 +00:00
Sam Clegg
2ccba8f08a Reland "[WebAssembly] Add visibility flag to Wasm symbol flags""
Original change was rL319488.

This was reverted rL319602 due to a gcc 7.1 warning.

Differential Revision: https://reviews.llvm.org/D40772

llvm-svn: 319626
2017-12-03 01:19:23 +00:00
Matt Arsenault
a9c9cf456e Fix typo in emitted attribute name
Fixes build when using this attribute combination
on an intrinsic.

llvm-svn: 319625
2017-12-03 00:03:01 +00:00
Craig Topper
d3015d65a9 [ValueTracking] Pass only a single lambda to computeKnownBitsFromShiftOperator by using KnownBits struct instead of separate APInts. NFCI
llvm-svn: 319624
2017-12-02 23:42:17 +00:00
Yaxun Liu
c23a93c71f CodeGen: Fix pointer info in SplitVecOp_EXTRACT_VECTOR_ELT/SplitVecRes_INSERT_VECTOR_ELT
Two issues found when doing codegen for splitting vector with non-zero alloca addr space:

DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT/SplitVecOp_EXTRACT_VECTOR_ELT uses dummy pointer info for creating
SDStore. Since one pointer operand contains multiply and add, InferPointerInfo is unable to
infer the correct pointer info, which ends up with a dummy pointer info for the target to lower
store and results in isel failure. The fix is to introduce MachinePointerInfo::getUnknownStack to
represent MachinePointerInfo which is known in alloca address space but without other information.

TargetLowering::getVectorElementPointer uses value type of pointer in addr space 0 for
multiplication of index and then add it to the pointer. However the pointer may be in an addr
space which has different size than addr space 0. The fix is to use the pointer value type for
index multiplication.

Differential Revision: https://reviews.llvm.org/D39758

llvm-svn: 319622
2017-12-02 22:13:22 +00:00
Don Hinton
2486515d54 [cmake] Re-commit: Remove redundant call to cmake when building host tools.
Also pass CMAKE_(C|CXX)_COMPILER to add_custom_command.

Summary:
Remove the redundant, config-time call to cmake when
building host tools for cross compiles or optimized tablegen..

The config-time call to cmake is redundant because it will always get
called again when the CONFIGURE_LLVM_${target_name} target fires at
build-time.  This speeds up initial configuration, but has no affect
on build behavior.

Differential Revision: https://reviews.llvm.org/D40229

llvm-svn: 319620
2017-12-02 19:12:38 +00:00
Simon Atanasyan
4e543466be [llvm-readobj] Remove redundant local variables to reduce the code. NFC
llvm-svn: 319617
2017-12-02 13:06:40 +00:00
Simon Atanasyan
b560f07537 [llvm-readobj] Print static MIPS GOT
If a linked binary file contains a dynamic section, the GOT layout
defined by the dynamic section entries. In a statically linked file
the GOT is just a series of entries. This change teaches `llvm-readobj`
to print the GOT in that case. That provides a feature parity with GNU
`readelf`.

llvm-svn: 319616
2017-12-02 13:06:35 +00:00
Simon Atanasyan
8105705153 [llvm-readobj] Delete unused method argument. NFC
llvm-svn: 319615
2017-12-02 13:06:27 +00:00
Simon Pilgrim
87e9a74fb7 [X86][SSE] Cleanup float/int conversion scheduler itinerary classes
Makes it easier to grok where each is supposed to be used, mainly useful for adding to the AVX512 instructions but hopefully can be used more in SSE/AVX as well.

llvm-svn: 319614
2017-12-02 12:27:44 +00:00
Craig Topper
9cdd6476d4 [X86] Fix copy paste mistake in test case for r319612.
llvm-svn: 319613
2017-12-02 08:39:02 +00:00
Craig Topper
7135686104 [X86] Teach the assembler to support %db8-%db15 as aliases for %dr8-%dr15.
llvm-svn: 319612
2017-12-02 08:27:46 +00:00
Craig Topper
8d65510314 [X86] Support %dr8-%dr15 in the assembler.
Apparently I failed to make this work when I fixed it in the disassembler way back in r224862.

llvm-svn: 319611
2017-12-02 08:27:45 +00:00
Martell Malone
34f65497f3 CMAKE: help CheckAtomic find check_library_exists
lldb fails to build standalone on x86

-- Performing Test HAVE_CXX_ATOMICS64_WITHOUT_LIB - Failed
CMake Error at CheckAtomic.cmake:66 (check_library_exists):
  Unknown CMake command "check_library_exists".
Call Stack (most recent call first):
  LLDBStandalone.cmake:90 (include)
CMakeLists.txt:3 (include)

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D40220

llvm-svn: 319610
2017-12-02 07:17:01 +00:00
Tatyana Krasnukha
ea3c2504e7 [ARC] Add instruction subset for the ARC backend.
Reviewers: petecoup, kparzysz

Reviewed By: petecoup

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D37983

llvm-svn: 319609
2017-12-02 05:25:17 +00:00
Nirav Dave
a16177fcd8 [DAG][AArch64] Disable post-legalization store
Disable post-legalization store for AArch64 backend which is causing
errors out-of-tree.

llvm-svn: 319607
2017-12-02 04:01:26 +00:00
Heejin Ahn
6aa6de8e58 [WebAssembly] Revert r319488 "Add visibility flag to Wasm symbol flags"
This patch reportedly broke one of LLVM bots (ubuntu-gcc7.1-werror).

See http://lab.llvm.org:8011/builders/ubuntu-gcc7.1-werror/builds/3369 for
details.

llvm-svn: 319602
2017-12-02 02:05:06 +00:00
Matt Morehouse
9d5c56d7ba Revert "[X86] Improvement in CodeGen instruction selection for LEAs."
This reverts r319543, due to ASan bot breakage.

llvm-svn: 319591
2017-12-01 22:20:26 +00:00
Kostya Serebryany
66b53a5db2 [libFuzzer] add a flag -malloc_limit_mb
llvm-svn: 319590
2017-12-01 22:12:04 +00:00
Jessica Paquette
9b65a2fe70 [MachineOutliner] NFC: Throw out self-intersections on candidates early
Currently, the outliner considers candidates that intersect with themselves in
the candidate pruning step. That is, candidates of the form "AA" in ranges like
"AAAAAA". In that range, it looks like there are 5 instances of "AA" that could
possibly be outlined, and that's considered in the benefit calculation.

However, only at most 3 instances of "AA" could ever be outlined in "AAAAAA".
Thus, it's possible to pass through "AA" to the candidate selection step even
though it's *never* the case that "AA" could be outlined. This makes it so that
when we find candidates, we consider only non-overlapping occurrences of that
candidate.

llvm-svn: 319588
2017-12-01 21:56:56 +00:00
Nirav Dave
eaaccfe544 [DAG][ARM] Revert "Reenable post-legalize store merge"
due to failures in AArch and ARM code gen.

llvm-svn: 319587
2017-12-01 21:55:47 +00:00
Jake Ehrlich
9a7dac2fce [MC] Handle unknown literal register numbers in .cfi_* directives
r230670 introduced a step to map EH register numbers to standard
DWARF register numbers. This failed to consider the case when a
user .cfi_* directive uses an integer literal rather than a
register name, to specify a DWARF register number that has no
corresponding LLVM register number (e.g. a special register that
the compiler and assembler have no name for).

Fixes PR34028.

Patch by Roland McGrath

Differential Revision: https://reviews.llvm.org/D36493

llvm-svn: 319586
2017-12-01 21:44:27 +00:00
Philip Reames
ffc60424d9 [IndVars] Fix a bug introduced in r317012
Turns out we can have comparisons which are indirect users of the induction variable that we can make invariant.  In this case, there is no loop invariant value contributing and we'd fail an assert.

The test case was found by a java fuzzer and reduced.  It's a real cornercase.  You have to have a static loop which we've already proven only executes once, but haven't broken the backedge on, and an inner phi whose result can be constant folded by SCEV using exit count reasoning but not proven by isKnownPredicate.  To my knowledge, only the fuzzer has hit this case.

llvm-svn: 319583
2017-12-01 20:57:19 +00:00