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Commit Graph

157413 Commits

Author SHA1 Message Date
Craig Topper
4a0dc124f3 [X86] Promote fp_to_sint v16f32->v16i16/v16i8 to avoid scalarization.
llvm-svn: 319266
2017-11-29 00:32:09 +00:00
Zachary Turner
04cc391642 Fix a warning.
llvm-svn: 319263
2017-11-29 00:13:44 +00:00
Adam Nemet
a8d567ec8e Revert "Add opt-viewer testing"
This reverts commit r319188.

Breaks when c++filt is not available.

llvm-svn: 319262
2017-11-29 00:10:48 +00:00
Craig Topper
a7d54728f8 [X86] Add test cases for fptosi v16f32->v16i8/v16i16 to show scalarization.
llvm-svn: 319261
2017-11-29 00:02:22 +00:00
Zachary Turner
02e8e3f33d [NFC] Minor cleanups in CodeView TypeTableBuilder.
llvm-svn: 319260
2017-11-28 23:57:13 +00:00
Craig Topper
7453e1fa7f [X86] Mark ISD::FP_TO_UINT v16i8/v16i16 as Promote under AVX512 instead of legal. Fix infinite loop in op legalization when promotion requires 2 steps.
Previously we had an isel pattern to add the truncate. Instead use Promote to add the truncate to the DAG before isel.

The Promote legalization code had to be updated to prevent an infinite loop if promotion took multiple steps because it wasn't remembering the previously tried value.

llvm-svn: 319259
2017-11-28 23:56:02 +00:00
Craig Topper
ddc40165bf [X86] Regenerate avx512-schedule test.
For some reason some sqrt instructions were missing the scheduling comments.

llvm-svn: 319258
2017-11-28 23:55:59 +00:00
Matt Arsenault
170d2ed287 AMDGPU: Enable IPRA
llvm-svn: 319256
2017-11-28 23:40:12 +00:00
Simon Pilgrim
7a4d895cdc [X86] Tag CLFLUSHOPT with same scheduling behaviour as CLFLUSH
llvm-svn: 319253
2017-11-28 23:25:42 +00:00
Daniel Sanders
88b4a0878a [globalisel][tablegen] Fix PR35375 by sign-extending the table value to match getConstantVRegVal()
Summary:
From the bug report:
> The problem is that it fails when trying to compare -65536 (or 4294901760) to 0xFFFF,0000. This is because the
> constant in the instruction is sign extended to 64 bits (0xFFFF,FFFF,FFFF,0000) and then compared to the non
> extended 64 bit version expected by TableGen.
> 
> In contrast, the DAGISelEmitter generates special code for AND immediates (OPC_CheckAndImm), which does not
> sign extend.

This patch doesn't introduce the special case for AND (and OR) immediates since the majority of it is related to handling known bits that have no effect on the result and GlobalISel doesn't detect known-bits at this time. Instead this patch just ensures that the immediate is extended consistently on both sides of the check.

Thanks to Diana Picus for the detailed bug report.

Reviewers: rovka

Reviewed By: rovka

Subscribers: kristof.beyls, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D40532

llvm-svn: 319252
2017-11-28 23:18:54 +00:00
Simon Pilgrim
542dbb0bec [X86] Add CLFLUSHOPT schedule tests
llvm-svn: 319250
2017-11-28 23:12:12 +00:00
Simon Pilgrim
12dfcfe0b1 [X86][SSE] Add SSE_SHUFP OpndItins
Update multi-classes to take the scheduling OpndItins instead of hard coding it.

Will be reused in the AVX512 equivalents.

llvm-svn: 319249
2017-11-28 23:09:18 +00:00
Simon Pilgrim
4850e200a0 [X86] Test clflushopt intrinsic on 32 and 64-bit targets
llvm-svn: 319247
2017-11-28 23:04:42 +00:00
Simon Pilgrim
9e6ca21eca [X86][SSE] Add SSE_UNPCK/SSE_PUNPCK OpndItins
Update multi-classes to take the scheduling OpndItins instead of hard coding it.

Will be reused in the AVX512 equivalents.

llvm-svn: 319245
2017-11-28 22:55:08 +00:00
Simon Pilgrim
3e9942c3b8 [X86][SSE] Use SSE_PACK OpndItins in PACKSS/PACKUS instruction definitions
Update multi-classes to take the scheduling OpndItins instead of hard coding it.

SSE_PACK will be reused in the AVX512 equivalents.

llvm-svn: 319243
2017-11-28 22:47:45 +00:00
Adam Nemet
473eb94bec Remove this test
After r319235, we no longer generate this remark.

llvm-svn: 319242
2017-11-28 22:39:38 +00:00
Simon Pilgrim
79c0ba6d94 Fix VS2017 narrowing conversion warning. NFCI
llvm-svn: 319240
2017-11-28 22:32:43 +00:00
Craig Topper
a16a5768e1 [X86] Remove unused variable.
llvm-svn: 319239
2017-11-28 22:28:23 +00:00
Adam Nemet
4a462917d8 Demote this opt remark to DEBUG.
From a random opt-stat output:

Top 10 remarks:
  tailcallelim/tailcall          53%
  inline/AlwaysInline            13%
  gvn/LoadClobbered              13%
  inline/Inlined                  8%
  inline/TooCostly                2%
  inline/NoDefinition             2%
  licm/LoadWithLoopInvariantAddressInvalidated  2%
  licm/Hoisted                    1%
  asm-printer/InstructionCount    1%
  prologepilog/StackSize          1%

llvm-svn: 319235
2017-11-28 22:11:00 +00:00
Craig Topper
6b120a1adf [X86] Remove code from combineUIntToFP that tried to favor UINT_TO_FP if legal when zero extending from vXi8/vX816.
The UINT_TO_FP is immediately converted to SINT_TO_FP when the node is re-evaluated because we'll detect that the sign bit is zero.

llvm-svn: 319234
2017-11-28 22:08:51 +00:00
Craig Topper
0daab52721 [X86] Remove custom lowering for uint_to_fp from vXi8/vXi16.
We have a DAG combine that uses a zero extend that should prevent this from ever occurring now.

llvm-svn: 319233
2017-11-28 22:08:48 +00:00
Daniel Sanders
ce08391be8 [globalisel][tablegen] Add support for importing G_ATOMIC_CMPXCHG, G_ATOMICRMW_* rules from SelectionDAG.
GIM_CheckNonAtomic has been replaced by GIM_CheckAtomicOrdering to allow it to support a wider
range of orderings. This has then been used to import patterns using nodes such
as atomic_cmp_swap, atomic_swap, and atomic_load_*.

llvm-svn: 319232
2017-11-28 22:07:05 +00:00
Adrian Prantl
ee6ecd60f5 SROA: Don't create variable fragments that are outside of the variable.
An alloca may be larger than a variable that is described to be stored
there. Don't create a dbg.value for fragments that are outside of the
variable.

This fixes PR35447.
https://bugs.llvm.org/show_bug.cgi?id=35447

llvm-svn: 319230
2017-11-28 21:30:38 +00:00
Don Hinton
57f9a6b164 [cmake] Pass LLVM_USE_LINKER flag when building host tools, e.g.,
LLVM_OPTIMIZED_TABLEGEN=ON, and not crosscompiling.

Differential Revision: https://reviews.llvm.org/D39734

llvm-svn: 319228
2017-11-28 21:23:30 +00:00
Alexey Bataev
6450563023 [SLP] Additional test for PR35354, NFC.
llvm-svn: 319224
2017-11-28 20:48:24 +00:00
Mandeep Singh Grang
8acd316e73 [Hexagon] Use stable sort for HexagonShuffler to remove non-deterministic ordering
Summary:
This fixes failures in the following tests uncovered by D39245:
        LLVM :: CodeGen/Hexagon/args.ll
        LLVM :: CodeGen/Hexagon/constp-extract.ll
        LLVM :: CodeGen/Hexagon/expand-condsets-basic.ll
        LLVM :: CodeGen/Hexagon/gp-rel.ll
        LLVM :: CodeGen/Hexagon/packetize_cond_inst.ll
        LLVM :: CodeGen/Hexagon/simple_addend.ll
        LLVM :: CodeGen/Hexagon/swp-stages4.ll
        LLVM :: CodeGen/Hexagon/swp-vmult.ll
        LLVM :: CodeGen/Hexagon/swp-vsum.ll
        LLVM :: MC/Hexagon/align.s
        LLVM :: MC/Hexagon/asmMap.s
        LLVM :: MC/Hexagon/dis-duplex-p0.s
        LLVM :: MC/Hexagon/double-vector-producer.s
        LLVM :: MC/Hexagon/inst_select.ll
        LLVM :: MC/Hexagon/instructions/j.s

Reviewers: colinl, kparzysz, adasgupt, slarin

Reviewed By: kparzysz

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D40227

llvm-svn: 319223
2017-11-28 20:48:10 +00:00
Daniel Sanders
ded67ff6bb [aarch64][globalisel] Add missing tests from r319216
llvm-svn: 319220
2017-11-28 20:27:59 +00:00
Sean Fertile
4a7b507243 [PowerPC] Allow tail calls of fastcc functions from C CallingConv functions.
Allow fastcc callees to be tail-called from ccc callers.

Differential Revision: https://reviews.llvm.org/D40355

llvm-svn: 319218
2017-11-28 20:25:58 +00:00
Daniel Sanders
cd1fb2fd55 [aarch64][globalisel] Define G_ATOMIC_CMPXCHG and G_ATOMICRMW_* and make them legal
The IRTranslator cannot generate these instructions at the moment so there's no
issue with not having implemented ISel for them yet. D40092 will add
G_ATOMIC_CMPXCHG_WITH_SUCCESS and G_ATOMICRMW_* to the IRTranslator and a
further patch will add support for lowering G_ATOMIC_CMPXCHG_WITH_SUCCESS into
G_ATOMIC_CMPXCHG with an external success check via the `Lower` action.

The separation of G_ATOMIC_CMPXCHG_WITH_SUCCESS and G_ATOMIC_CMPXCHG is
to import SelectionDAG rules while still supporting targets that prefer to
custom lower the original LLVM-IR-like operation.

llvm-svn: 319216
2017-11-28 20:21:15 +00:00
Mandeep Singh Grang
4adb0a62b6 [SelectionDAG] Make sorting predicate stronger to remove non-deterministic ordering
Summary:
Recommitting this with the correct sorting predicate. The Low field of Clusters is a ConstantInt and
cannot be directly compared. So we needed to invoke slt (signed less than) to compare correctly.

This fixes failures in the following tests uncovered by D39245:

LLVM :: CodeGen/ARM/ifcvt3.ll
LLVM :: CodeGen/ARM/switch-minsize.ll
LLVM :: CodeGen/X86/switch.ll
LLVM :: CodeGen/X86/switch-bt.ll
LLVM :: CodeGen/X86/switch-density.ll

Reviewers: hans, fhahn

Reviewed By: hans

Subscribers: aemerson, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D40541

llvm-svn: 319210
2017-11-28 19:55:54 +00:00
Simon Pilgrim
8b94bfe4a5 [X86][SSE] Add SSE_HADDSUB/SSE_PABS/SSE_PALIGN OpndItins
Update multi-classes to take the scheduling OpndItins instead of hard coding it.

Will be reused in the AVX512 equivalents.

llvm-svn: 319209
2017-11-28 19:39:47 +00:00
Craig Topper
219d029650 [X86] In lowerVectorShuffleAsElementInsertion, if were able to find a scalar i8 or i16 and need to zero extend it, make sure we use a vXi32 type of the full vector width.
Previously, this was hardcoded to v4i32, but if the input type is 256 bits we need to use v8i32.

Fixes PR35443

llvm-svn: 319208
2017-11-28 19:25:45 +00:00
Francis Visoiu Mistrih
4000378d4b [CodeGen] Fix doxygen \file comment style
llvm-svn: 319207
2017-11-28 19:23:39 +00:00
Francis Visoiu Mistrih
708b5d7b59 [CodeGen] Fix doxygen
llvm-svn: 319206
2017-11-28 19:15:46 +00:00
Sanjay Patel
e6f05aab66 [InstCombine] auto-generate complete test checks; NFC
llvm-svn: 319205
2017-11-28 19:13:23 +00:00
Krzysztof Parzyszek
1d202524c0 [Hexagon] Make sure to zero-extend bytes before building a vector
llvm-svn: 319204
2017-11-28 19:13:17 +00:00
Sanjay Patel
aa4475e9e8 [InstCombine] auto-generate complete test checks; NFC
llvm-svn: 319203
2017-11-28 19:07:28 +00:00
Daniel Sanders
17578579a6 [mir] Print/Parse both MOLoad and MOStore when they occur together.
Summary:
They're not always mutually exclusive. read-modify-write atomics are both
at the same time. One example of this is the SWP instructions on AArch64.
Another example is GlobalISel's G_ATOMICRMW_* generic instructions which
will be added in a later patch.

Reviewers: arphaman, aemerson

Reviewed By: aemerson

Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D40157

llvm-svn: 319202
2017-11-28 18:57:02 +00:00
Rafael Espindola
fc4818e12a Fix non assert build warnings.
llvm-svn: 319200
2017-11-28 18:50:08 +00:00
Hans Wennborg
5508a81574 EntryExitInstrumenter: set DebugLocs on the inserted call instructions (PR35412)
Apparently the verifier requires that inlineable calls in a function
with debug info have debug locations.

llvm-svn: 319199
2017-11-28 18:44:26 +00:00
Zachary Turner
4202759d3b [CodeView] Refactor / Rewrite TypeSerializer and TypeTableBuilder.
The motivation behind this patch is that future directions require us to
be able to compute the hash value of records independently of actually
using them for de-duplication.

The current structure of TypeSerializer / TypeTableBuilder being a
single entry point that takes an unserialized type record, and then
hashes and de-duplicates it is not flexible enough to allow this.

At the same time, the existing TypeSerializer is already extremely
complex for this very reason -- it tries to be too many things. In
addition to serializing, hashing, and de-duplicating, ti also supports
splitting up field list records and adding continuations. All of this
functionality crammed into this one class makes it very complicated to
work with and hard to maintain.

To solve all of these problems, I've re-written everything from scratch
and split the functionality into separate pieces that can easily be
reused. The end result is that one class TypeSerializer is turned into 3
new classes SimpleTypeSerializer, ContinuationRecordBuilder, and
TypeTableBuilder, each of which in isolation is simple and
straightforward.

A quick summary of these new classes and their responsibilities are:

- SimpleTypeSerializer : Turns a non-FieldList leaf type into a series of
  bytes. Does not do any hashing. Every time you call it, it will
  re-serialize and return bytes again. The same instance can be re-used
  over and over to avoid re-allocations, and in exchange for this
  optimization the bytes returned by the serializer only live until the
  caller attempts to serialize a new record.

- ContinuationRecordBuilder : Turns a FieldList-like record into a series
  of fragments. Does not do any hashing. Like SimpleTypeSerializer,
  returns references to privately owned bytes, so the storage is
  invalidated as soon as the caller tries to re-use the instance. Works
  equally well for LF_FIELDLIST as it does for LF_METHODLIST, solving a
  long-standing theoretical limitation of the previous implementation.

- TypeTableBuilder : Accepts sequences of bytes that the user has already
  serialized, and inserts them by de-duplicating with a hash table. For
  the sake of convenience and efficiency, this class internally stores a
  SimpleTypeSerializer so that it can accept unserialized records. The
  same is not true of ContinuationRecordBuilder. The user is required to
  create their own instance of ContinuationRecordBuilder.

Differential Revision: https://reviews.llvm.org/D40518

llvm-svn: 319198
2017-11-28 18:33:17 +00:00
Simon Pilgrim
456966cb64 [X86][X87] Tag FP_TO_INT_IN_MEM pseudos with hasNoSchedulingInfo
We don't need scheduling info for pseudos

llvm-svn: 319197
2017-11-28 18:10:29 +00:00
Francis Visoiu Mistrih
2f8e427cd6 [CodeGen] Separate MachineOperand implementation from MachineInstr
Move the implementation to its own file.

Differential Revision: https://reviews.llvm.org/D40419

llvm-svn: 319194
2017-11-28 17:58:43 +00:00
Francis Visoiu Mistrih
5ce551fce8 [CodeGen] Cleanup MachineOperand
* clang-format
* move doxygen from the implementation to headers
* remove duplicate doxygen

llvm-svn: 319193
2017-11-28 17:58:38 +00:00
Konstantin Zhuravlyov
ec13d639b3 AMDGPU: Add num spilled s/vgprs to metadata
This was requested by tools.

Differential Revision: https://reviews.llvm.org/D40321

llvm-svn: 319192
2017-11-28 17:51:08 +00:00
Adam Nemet
206e1448f6 Add opt-viewer testing
Detects whether we have the Python modules (pygments, yaml) required by
opt-viewer and hooks this up to REQUIRES.

This fixes https://bugs.llvm.org/show_bug.cgi?id=34129 (the lack of opt-viewer
testing).

It's also related to https://github.com/apple/swift/pull/12938 and the idea is
to expose LLVM_HAVE_OPT_VIEWER_MODULES to the Swift cmake.

Differential Revision: https://reviews.llvm.org/D40202

llvm-svn: 319188
2017-11-28 17:26:28 +00:00
Francis Visoiu Mistrih
961f3df27b [CodeGen] Print register names in lowercase in both MIR and debug output
As part of the unification of the debug format and the MIR format,
always print registers as lowercase.

* Only debug printing is affected. It now follows MIR.

Differential Revision: https://reviews.llvm.org/D40417

llvm-svn: 319187
2017-11-28 17:15:09 +00:00
Dan Gohman
07539b2a74 [WebAssembly] Support bitcasted function addresses with varargs.
Generalize FixFunctionBitcasts to handle varargs functions. This in
particular fixes the case where clang bitcasts away a varargs when
calling a K&R-style function.

This avoids interacting with tricky ABI details because it operates
at the LLVM IR level before varargs ABI details are exposed.

This fixes PR35385.

llvm-svn: 319186
2017-11-28 17:15:03 +00:00
Matt Arsenault
7cb9a92f9b DAG: Legalize truncstores to illegal int types
Truncate to a legal int type, and produce a new
truncstore from a narrower type.

llvm-svn: 319185
2017-11-28 17:11:30 +00:00
Simon Pilgrim
fd18f19969 [X86][X87] Tag FTST x87 instruction scheduler class
Looking through Agner, FTST is very similar to generic float compare behaviour, so I've added them to the existing IIC_FCOMI (WriteFAdd) tags.

llvm-svn: 319184
2017-11-28 16:57:20 +00:00