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Commit Graph

214529 Commits

Author SHA1 Message Date
Michael Holman
e4e8dcd990 [CodeView] Add CodeView support for PGO debug information
This change adds debug information about whether PGO is being used or
not.

Microsoft performance tooling (e.g. xperf, WPA) uses this information to
show whether functions are optimized with PGO or not, as well as whether
PGO information is invalid.

This information is useful for validating whether training scenarios are
providing good coverage of real world scenarios, showing if profile data
is out of date, etc.

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D99994
2021-04-21 15:29:19 -07:00
Craig Topper
c445dfb378 [RISCV] Cleanup up the spec version references around fmaxnum/fminnum.
This previously made references to 2.3-draft which was a short
lived version number in 2017. It was replaced by date based
versions leading up to ratification.

This patch uses the latest ratified version number and just says
what the behavior is. Nothing here is in flux.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D100878
2021-04-21 14:50:29 -07:00
Craig Topper
2f23110bec [RISCV] Temporary in vmsge(u).vx pseudo instructions can't be V0.
This was checked in some asserts, but not enforced by the
instruction matching.

There's still a second bug that we don't check that vt and vd
are different registers, but that will require custom checking.

Differential Revision: https://reviews.llvm.org/D100928
2021-04-21 14:50:29 -07:00
Petr Hosek
92218c28cd [MC] Use COMDAT for LSDA only if IR comdat type is any
This fixed issue introduced in 16af97393346ad636298605930a8b503a55eb40a
and 796feb61637c407aefcc0d462f24a1cc41f350d8.

Differential Revision: https://reviews.llvm.org/D100909
2021-04-21 14:41:39 -07:00
Olle Fredriksson
16a7ccaf6b [MemCpyOpt] Allow variable lengths in memcpy optimizer
This makes the memcpy-memcpy and memcpy-memset optimizations work for
variable sizes as long as they are equal, relaxing the old restriction
that they are constant integers. If they're not equal, the old
requirement that they are constant integers with certain size
restrictions is used.

The implementation works by pushing the length tests further down in the
code, which reveals some places where it's enough that the lengths are
equal (but not necessarily constant).

Differential Revision: https://reviews.llvm.org/D100870
2021-04-21 23:23:38 +02:00
Arthur Eubanks
8a2dd1008a [Evaluator] Bitcast result of pointer stripping
Trying to evaluate a GEP would assert with
  "Ty == cast<PointerType>(C->getType()->getScalarType())->getElementType()"
because the type of the pointer we would evaluate the GEP argument to
would be a different type than the GEP was expecting. We should treat
pointer stripping as a bitcast.

The test adds a redundant GEP that would crash due to type mismatch.

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D100970
2021-04-21 13:32:29 -07:00
Alexey Bataev
7d8daf5c45 [SLP]Add a test with broadcast shuffle kind in SLP, NFC. 2021-04-21 13:16:31 -07:00
Arthur Eubanks
12af0f159d [LLParser] Print mismatched types in error message
Helps with debugging invalid handcrafted IR.

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D100990
2021-04-21 13:10:37 -07:00
Dávid Bolvanský
655dee38a7 [LoopIdiom] Added testcase from PR44378; NFC 2021-04-21 22:00:32 +02:00
Nikita Popov
7d32930751 Revert "[InstCombine] Fold multiuse shr eq zero"
This reverts commit 9423f78240a216e3f38b394a41fe3427dee22c26.

A performance regression with this patch has been reported at
https://reviews.llvm.org/rG9423f78240a2#990953. Reverting for now.
2021-04-21 21:40:52 +02:00
sstefan1
c15c1eb8f9 [FuncAttrs] Don't infer willreturn for nonexact definitions
Discovered during attributor testing comparing stats with
and without the attributor. Willreturn should not be inferred
for nonexact definitions.

Differential Revision: https://reviews.llvm.org/D100988
2021-04-21 21:26:09 +02:00
sstefan1
b6d664ee22 [SimplifyLibCalls] Don't change alignment when creating memset
Fix for PR49984
This was discovered during Attributor testing.
Memset was always created with alignment of 1
and in case when strncpy alignment was changed
it triggered an assertion in the AttrBuilder.
Memset will now be created with appropriate alignment.

Differential Revision: https://reviews.llvm.org/D100875
2021-04-21 20:34:13 +02:00
Sanjay Patel
b3bc645e79 [InstSimplify] generalize ctlz-of-shifted-constant
https://alive2.llvm.org/ce/z/zWL_VQ
2021-04-21 14:23:55 -04:00
Sanjay Patel
6d9b6618de [InstSimplify] add tests for ctlz-of-shift-constant; NFC 2021-04-21 14:23:55 -04:00
Simon Pilgrim
411f75a025 [X86][SSE] getFauxShuffleMask - don't decode OR(SHUFFLE,SHUFFLE) containing UNDEFs. (PR50049)
PR50049 demonstrated an infinite loop between OR(SHUFFLE,SHUFFLE) <-> BLEND(SHUFFLE,SHUFFLE) patterns.

The UNDEF elements were allowing a combined shuffle mask to be widened which lost the undef element, resulting us needing to use the BLEND pattern (as the undef element would need to be zero for the OR pattern). But then bitcast folds would re-expose the undef element allowing us to use OR again.....
2021-04-21 18:47:00 +01:00
Hongtao Yu
bd70c1c8f2 [CSSPGO] Exclude pseudo probe from slotindex verification. 2021-04-21 09:17:12 -07:00
Nico Weber
fe1591ee8e [gn build] add llvm-profgen to gn build
Didn't notice it missing due to https://reviews.llvm.org/D89707#2705110
2021-04-21 11:50:41 -04:00
LLVM GN Syncbot
542098407f [gn build] Port 97e383aa061b 2021-04-21 15:39:33 +00:00
Stanislav Mekhanoshin
83ba5fd3fb [AMDGPU] Lower regbanks reassign threshold to 15000
Let it work on a very small kernels only. Measurements showed
the performance benefit is not worth the compile time.

Differential Revision: https://reviews.llvm.org/D100904
2021-04-21 08:34:11 -07:00
dfukalov
838d1d55de [TTI] NFC: Change getVectorSplitCost to return InstructionCost
This patch migrates the TTI cost interfaces to return an InstructionCost.

See this patch for the introduction of the type: https://reviews.llvm.org/D91174
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2020-November/146408.html

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D100952
2021-04-21 17:32:02 +03:00
Anirudh Prasad
129d906140 [AsmParser][ms][X86] Fix possible misbehaviour in parsing of special tokens at start of string.
- Previously, https://reviews.llvm.org/D72680 introduced a new attribute called `AllowSymbolAtNameStart` (in relation to the MAsmParser changes) in `MCAsmInfo.h` which (according to the comment in the header) allows the following behaviour:

```
  /// This is true if the assembler allows $ @ ? characters at the start of
  /// symbol names. Defaults to false.
```

- However, the usage of this field in AsmLexer.cpp doesn't seem completely accurate* for a couple of reasons.

```
  default:
    if (MAI.doesAllowSymbolAtNameStart()) {
      // Handle Microsoft-style identifier: [a-zA-Z_$.@?][a-zA-Z0-9_$.@#?]*
      if (!isDigit(CurChar) &&
          isIdentifierChar(CurChar, MAI.doesAllowAtInName(),
                           AllowHashInIdentifier))
        return LexIdentifier();
    }
```

1. The Dollar and At tokens, when occurring at the start of the string, are treated as separate tokens (AsmToken::Dollar and AsmToken::At respectively) and not lexed as an Identifier.
2. I'm not too sure why `MAI.doesAllowAtInName()` is used when `AllowAtInIdentifier` could be used. For X86 platforms, afaict, this shouldn't be an issue, since the `CommentString` attribute isn't "@". (alternatively the call to the setter can be set anywhere else as needed). The `AllowAtInName` does have an additional important meaning, but in the context of AsmLexer, shouldn't mean anything different compared to `AllowAtInIdentifier`

My proposal is the following:

- Introduce 3 new fields called `AllowQuestionTokenAtStartOfString`, `AllowDollarTokenAtStartOfString` and `AllowAtTokenAtStartOfString` in MCAsmInfo.h which will encapsulate the previously documented behaviour of "allowing $, @, ? characters at the start of symbol names")
- Introduce these fields where "$", "@" are lexed, and treat them as identifiers depending on whether `Allow[Dollar|At]TokenAtStartOfString` is set.
- For the sole case of "?", append it to the existing logic for treating a "default" token as an Identifier.

z/OS (HLASM) will also make use of some of these fields in follow up patches.

completely accurate* - This was based on the comments and the intended behaviour the code. I might have completely misinterpreted it, and if that is the case my sincere apologies. We can close this patch if necessary, if there are no changes to be made :)

Depends on https://reviews.llvm.org/D99374

Reviewed By: Jonathan.Crowther

Differential Revision: https://reviews.llvm.org/D99889
2021-04-21 10:21:09 -04:00
Nico Weber
25b1225bca [Support] Don't include VirtualFileSystem.h in CommandLine.h
CommandLine.h is indirectly included in ~50% of TUs when building
clang, and VirtualFileSystem.h is large.

(Already remarked by jhenderson on D70769.)

No behavior change.

Differential Revision: https://reviews.llvm.org/D100957
2021-04-21 10:19:01 -04:00
Simon Pilgrim
2f6d5a3c21 [PhaseOrdering] Add test case for PR45682
Ensures that the correct sequence of simplifycfg/instcombine/sroa reduce the IR to just a icmp+assume (which will be dropped in backend)
2021-04-21 15:07:00 +01:00
Simon Pilgrim
4edb18ca2b [MC] MCInstrDesc.h - remove unnecessary <string> include. NFCI. 2021-04-21 15:07:00 +01:00
Fraser Cormack
3d3fa3ed76 [SelectionDAG] Fix minor typo in ISDOpcodes.h. NFC 2021-04-21 14:38:07 +01:00
Caroline Concatto
547af41fa3 [AArch64][SVE] Fix crash with icmp+select
This patch changes the lowering of SELECT_CC from Legal to Expand for scalable
vector and adds support for scalable vectors in performSelectCombine.

When selecting the nodes to lower in visitSELECT it checks if it is possible to
use SELECT_CC in cases where SETCC is followed by SELECT. visistSELECT checks
if SELECT_CC is legal or custom to replace SELECT by SELECT_CC.
SELECT_CC used to be legal for scalable vector, so the node changes to
SELECT_CC. This used to crash the compiler as there is no support for SELECT_CC
with scalable vectors. So now the compiler lowers to VSELECT instead of
SELECT_CC.

Differential Revision: https://reviews.llvm.org/D100485
2021-04-21 14:16:27 +01:00
Matt Arsenault
4fb212a574 AMDGPU: Fix indirect tail calls
Fix a selection error on uniform callees, and use a regular call if
divergent.
2021-04-21 09:15:24 -04:00
David Green
118f1ecde3 [AArch64] Add and update reverse mask tests. NFC 2021-04-21 12:11:41 +01:00
Simon Tatham
49b1d59516 [ARM][Driver][Windows] Allow command-line upgrade to Armv8.
If you gave clang the options `--target=arm-pc-windows-msvc` and
`-march=armv8-a+crypto` together, the crypto extension would not be
enabled in the compilation, and you'd see the following warning
message suggesting that the 'armv8-a' had been ignored:

  clang: warning: ignoring extension 'crypto' because the 'armv7-a' architecture does not support it [-Winvalid-command-line-argument]

This happens because Triple::getARMCPUForArch(), for the Win32 OS,
unconditionally returns "cortex-a9" (an Armv7 CPU) regardless of
MArch, which overrides the architecture setting on the command line.

I don't think that the combination of Windows and AArch32 _should_
unconditionally outlaw the use of the crypto extension. MSVC itself
doesn't think so: you can perfectly well compile Thumb crypto code
using its AArch32-targeted compiler.

All the other default CPUs in the same switch statement are
conditional on a particular MArch setting; this is the only one that
returns a particular CPU _regardless_ of MArch. So I've fixed this one
by adding a condition, so that if you ask for an architecture *above*
v7, the default of Cortex-A9 no longer overrides it.

Reviewed By: mstorsjo

Differential Revision: https://reviews.llvm.org/D100937
2021-04-21 11:20:05 +01:00
Simon Pilgrim
2a2d25a7be [DAG] TargetLowering.cpp - breakup if-else chains where each block returns. NFCI.
Match style guide that requests that if+return blocks are separate.
2021-04-21 11:17:27 +01:00
Fraser Cormack
74ffc8e63c [DAGCombiner] Support all-ones/all-zeros SPLAT_VECTOR in more combines
This patch adds incrementally-better support for SPLAT_VECTOR in a
handful of vector combines by changing a few more
isBuildVectorAllOnes/isBuildVectorAllZeros to the equivalent
isConstantSplatVectorAllOnes/Zeros calls.

Reviewed By: paulwalker-arm

Differential Revision: https://reviews.llvm.org/D100851
2021-04-21 11:05:37 +01:00
Fraser Cormack
95fc7ab21d [RISCV] Further fixes for RVV stack offset computation
This patch fixes a case missed out by D100574, in which RVV scalable
stack offset computations may require three live registers in the case
where the offset's fixed component is 12 bits or larger and has a
scalable component.

Instead of adding an additional emergency spill slot, this patch further
optimizes the scalable stack offset computation sequences to reduce
register usage.

By emitting the sequence to compute the scalable component before the
fixed component, we can free up one scratch register to be reallocated
by the sequence for the fixed component. Doing this saves one register
and thus one additional emergency spill slot.

Compare:

    $x5 = LUI 1
    $x1 = ADDIW killed $x5, -1896
    $x1 = ADD $x2, killed $x1
    $x5 = PseudoReadVLENB
    $x6 = ADDI $x0, 50
    $x5 = MUL killed $x5, killed $x6
    $x1 = ADD killed $x1, killed $x5

versus:

    $x5 = PseudoReadVLENB
    $x1 = ADDI $x0, 50
    $x5 = MUL killed $x5, killed $x1
    $x1 = LUI 1
    $x1 = ADDIW killed $x1, -1896
    $x1 = ADD $x2, killed $x1
    $x1 = ADD killed $x1, killed $x5

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D100847
2021-04-21 10:51:07 +01:00
Martin Storsjö
4a1d40cba0 [llvm-rc] Try to fix the Preprocessor/llvm-rc.rc test on non arm/x86 architectures
When llvm-rc invokes clang for preprocessing, it uses a target
triple derived from the default target. The test verifies that
e.g. _WIN32 is defined when preprocessing.

If running clang with e.g. -target ppc64le-windows-msvc, that
particular arch/OS combination isn't hooked up, so _WIN32 doesn't
get defined in that configuration. Therefore, the preprocessing
test fails.

Instead make llvm-rc inspect the architecture of the default target.
If it's one of the known supported architectures, use it as such,
otherwise set a default one (x86_64). (Clang can run preprocessing
with an x86_64 target triple, even if the x86 backend isn't
enabled.)

Also remove superfluous llvm:: specifications on enums in llvm-rc.cpp.
2021-04-21 12:47:33 +03:00
Martin Storsjö
ae24723f0f [llvm-rc] Run clang to preprocess input files
Allow opting out from preprocessing with a command line argument.

Update tests to pass -no-preprocess to make it not try to use clang
(which isn't a build level dependency of llvm-rc), but add a test that
does preprocessing under clang/test/Preprocessor.

Update a few options to allow them both joined (as -DFOO) and separate
(-D BR), as rc.exe allows both forms of them.

With the verbose flag set, this prints the preprocessing command
used (which differs from what rc.exe does).

Tests under llvm/test/tools/llvm-rc only test constructing the
preprocessor commands, while tests under clang/test/Preprocessor test
actually running the preprocessor.

Differential Revision: https://reviews.llvm.org/D100755
2021-04-21 11:50:10 +03:00
Martin Storsjö
09f1330345 [llvm-cvtres] Reduce the set of dependencies of llvm-cvtres. NFC.
Don't use createBinary() but call the WindowsResource class directly.
The createBinary() function references all supported object file
types and ends up pulling way more from all the underlying libraries
than what is necessary.

This shrinks a stripped llvm-cvtres from 4.6 MB to 463 KB.

Differential Revision: https://reviews.llvm.org/D100833
2021-04-21 11:50:10 +03:00
David Sherwood
081c5cd9a4 [AArch64] Add instruction costs for FP_TO_UINT and FP_TO_SINT with half types
We were missing some instruction costs when converting vectors of
floating point half types into integers, so I've added those here.
I also manually generated assembly code for each FP->int case and
looked at the number of instructions generated, which meant
adjusting some of the existing costs too.

I've updated an existing test to reflect the new costs:

  Analysis/CostModel/AArch64/sve-fptoi.ll

Differential Revision: https://reviews.llvm.org/D99935
2021-04-21 09:39:45 +01:00
Christian Kühnel
a6b448f809 [NFC] fixed link in documentation 2021-04-21 10:17:03 +02:00
Yang Fan
0c89a953db [SCEV] Fix -Wunused-variable warning (NFC)
GCC warning:
```
/llvm-project/llvm/lib/Analysis/ScalarEvolution.cpp: In member function ‘const llvm::SCEV* llvm::ScalarEvolution::getLosslessPtrToIntExpr(const llvm::SCEV*, unsigned int)::SCEVPtrToIntSinkingRewriter::visitUnknown(const llvm::SCEVUnknown*)’:
/llvm-project/llvm/lib/Analysis/ScalarEvolution.cpp:1152:13: warning: unused variable ‘ExprPtrTy’ [-Wunused-variable]
 1152 |       Type *ExprPtrTy = Expr->getType();
      |             ^~~~~~~~~
```
2021-04-21 16:01:46 +08:00
Christian Kühnel
271e47c106 added section on CI system
Add documentation for working with the CI systems.

This is based on the discussion in the Infrastructure Working Group:
https://github.com/ChristianKuehnel/iwg-workspace/issues/37

Differential Revision: https://reviews.llvm.org/D97389
2021-04-21 09:59:41 +02:00
Nikita Popov
f8a60b9733 Revert "[InstSimplify] Bypass no-op and-mask, using known bits (PR49543)"
This reverts commit ea1a0d7c9ae3e5232a4163fc67efad4aabd51f2b.

While this is strictly more powerful, it is also strictly slower.
InstSimplify intentionally does not perform many folds that it
is allowed to perform, if doing so requires a KnownBits calculation
that will be repeated in InstCombine.

Maybe it's worthwhile to do this here, but that needs a more
explicitly stated motivation, evaluated in a review.
2021-04-21 09:55:25 +02:00
David Sherwood
1ea67899d6 [Docs] Fix formatting issue for llvm.experimental.stepvector in LangRef
The llvm.experimental.stepvector section was missing the '^^^' line
underneath the intrinsic name.
2021-04-21 08:42:40 +01:00
Zakk Chen
d233144dbc [RISCV][MC] Mask load should not have VMConstraint.
Add a test, dest register could be v0.

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D100825
2021-04-21 15:21:37 +08:00
Serge Pavlov
72eb7a3974 [RISCV] Introduce floating point control and state registers
New registers FRM, FFLAGS and FCSR was defined. They represent
corresponding system registers. The new registers are necessary to
properly order floating point instructions in non-default modes.

Differential Revision: https://reviews.llvm.org/D99083
2021-04-21 12:55:30 +07:00
serge-sans-paille
0241a57a8c Use SmallVector instead of std::vector to manage storage of llvm::BitVector
This is a follow-up to https://reviews.llvm.org/D100387.

std::vector is not the best storage container here. My local benchmark (counting
the number of instruction when compiling the sqlite3 amalgamation) yields the
following:

- std::vector<BitVector> -> 5,860,885,896
- SmallVector<BitWord, 0> -> 5,858,991,997
- SmallVector<BitWord> -> 5,817,679,224

Differential Revision: https://reviews.llvm.org/D100744
2021-04-21 07:31:28 +02:00
Arthur Eubanks
fa90b27f77 [NFC] Remove redundant InstCombinePass name 2021-04-20 22:23:07 -07:00
Max Kazantsev
1c29570e8c [Test] Add a negative unit test 2021-04-21 12:11:05 +07:00
Zi Xuan Wu
844e8b7b70 [NFC][CSKY] Resort the instruction description in td
Resort the instruction description in td to make it easy to upstream more instructions and add predicts later.
2021-04-21 12:36:07 +08:00
Craig Topper
550007c220 [RISCV] Add missing SEW=64 tests to vmslt-rv32.ll. NFC 2021-04-20 18:31:36 -07:00
George Balatsouras
8eaf3e2f22 [dfsan] Enable origin tracking with fast8 mode
All related instrumentation tests have been updated.

Reviewed By: stephan.yichao.zhao

Differential Revision: https://reviews.llvm.org/D100903
2021-04-20 18:10:32 -07:00
Adrian Prantl
2f75daf38f Make sure PHIElimination doesn't copy debug locations across basic blocks.
PHIElimination may insert copy instructions in multiple basic
blocks. Moving debug locations across basic block boundaries would be
misleading as illustrated by the test case.

rdar://75463656

Differential Revision: https://reviews.llvm.org/D100886
2021-04-20 17:03:29 -07:00