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116055 Commits

Author SHA1 Message Date
John Brawn
e70236adf8 [GVN] Invalidate cached info for phis when setting dead predecessors to undef
When GVN sets the incoming value for a phi to undef because the incoming block
is unreachable it needs to also invalidate the cached info for that phi in
MemoryDependenceAnalysis, otherwise later queries will return stale information.

Differential Revision: https://reviews.llvm.org/D51099

llvm-svn: 340529
2018-08-23 12:48:17 +00:00
Victor Leschuk
69aa3df088 [DWARF] Unify warning callbacks. NFC.
Both DWARFDebugLine and DWARFDebugAddr used the same callback mechanism
for handling recoverable errors. They both implemented similar warn() function
to be used as such callbacks.

In this revision we get rid of code duplication and move this warn() function
to DWARFContext as DWARFContext::dumpWarning().

Reviewers: lhames, jhenderson, aprantl, probinson, dblaikie, JDevlieghere

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D51033

llvm-svn: 340528
2018-08-23 12:43:33 +00:00
Florian Hahn
7540f22c19 [SCCP] Remove unused variable added in r340525.
llvm-svn: 340526
2018-08-23 11:17:59 +00:00
Florian Hahn
1e1573359c Recommit r333268: [IPSCCP] Use PredicateInfo to propagate facts from cmp instructions.
This version of the patch fixes cleaning up ssa_copy intrinsics, so it does not
crash for instructions in blocks that have been marked unreachable.

This patch updates IPSCCP to use PredicateInfo to propagate
facts to true branches predicated by EQ and to false branches
predicated by NE.

As a follow up, we should be able to extend it to also propagate additional
facts about nonnull.

Reviewers: davide, mssimpso, dberlin, efriedma

Reviewed By: davide, dberlin

Differential Revision: https://reviews.llvm.org/D45330

llvm-svn: 340525
2018-08-23 11:04:00 +00:00
Sven van Haastregt
f57c8889d5 [Support] Fix some Wundef warnings
For the _WIN32 macro, it is the definedness that matters rather than
the value.  Most uses of the macro already rely on the definedness.
This commit fixes the few remaining uses that relied on the value.

Differential Revision: https://reviews.llvm.org/D51105

llvm-svn: 340520
2018-08-23 09:42:58 +00:00
Alexander Richardson
ae19e5c0f7 Allow creating llvm::Function in non-zero address spaces
Most users won't have to worry about this as all of the
'getOrInsertFunction' functions on Module will default to the program
address space.

An overload has been added to Function::Create to abstract away the
details for most callers.

This is based on https://reviews.llvm.org/D37054 but without the changes to
make passing a Module to Function::Create() mandatory. I have also added
some more tests and fixed the LLParser to accept call instructions for
types in the program address space.

Reviewed By: bjope

Differential Revision: https://reviews.llvm.org/D47541

llvm-svn: 340519
2018-08-23 09:25:17 +00:00
Peter Collingbourne
5542bfdc97 Initialize the address-significance table fragment's layout order.
This fragment is created after layout, which is where the order
normally gets set.

Should fix a test failure under msan.

llvm-svn: 340516
2018-08-23 06:57:49 +00:00
Chandler Carruth
5645346620 [x86/retpoline] Split the LLVM concept of retpolines into separate
subtarget features for indirect calls and indirect branches.

This is in preparation for enabling *only* the call retpolines when
using speculative load hardening.

I've continued to use subtarget features for now as they continue to
seem the best fit given the lack of other retpoline like constructs so
far.

The LLVM side is pretty simple. I'd like to eventually get rid of the
old feature, but not sure what backwards compatibility issues that will
cause.

This does remove the "implies" from requesting an external thunk. This
always seemed somewhat questionable and is now clearly not desirable --
you specify a thunk the same way no matter which set of things are
getting retpolines.

I really want to keep this nicely isolated from end users and just an
LLVM implementation detail, so I've moved the `-mretpoline` flag in
Clang to no longer rely on a specific subtarget feature by that name and
instead to be directly handled. In some ways this is simpler, but in
order to preserve existing behavior I've had to add some fallback code
so that users who relied on merely passing -mretpoline-external-thunk
continue to get the same behavior. We should eventually remove this
I suspect (we have never tested that it works!) but I've not done that
in this patch.

Differential Revision: https://reviews.llvm.org/D51150

llvm-svn: 340515
2018-08-23 06:06:38 +00:00
Peter Collingbourne
6c085fb98b MC: Don't align COFF section contents.
Aligning section contents is not required, but only
recommended, by the specification. Microsoft's documentation says
(https://docs.microsoft.com/en-us/windows/desktop/debug/pe-format#section-table-section-headers):
"For object files, the value should be aligned on a 4-byte boundary
for best performance."

However, according to my measurements, aligning section contents has
a neutral to negative effect on performance.

I measured the median run time of 100 links of Chromium's
base_unittests on Linux with lld-link and on Windows with link.exe with
both aligned and unaligned sections. On Linux I didn't see a measurable
performance difference, and on Windows the link was slightly faster
with unaligned sections (presumably because on Windows the bottleneck
is I/O).

Also, the sections created by cl.exe are unaligned, so we should expect
tools to broadly accept unaligned sections.

Differential Revision: https://reviews.llvm.org/D51149

llvm-svn: 340514
2018-08-23 05:39:36 +00:00
Chandler Carruth
a4cb0d60d9 Revert r340508: [DebugInfo] Fix bug in LiveDebugVariables.
This patch's test case relies on debug prints which isn't generally an
OK way to test stuff in LLVM and fails whenever asserts aren't enabled.
I've send a heads-up to the commit and detailed comments on the review.

llvm-svn: 340513
2018-08-23 05:39:02 +00:00
David Bolvansky
4695717fdb [LibCalls] Added returned attribute to libcalls
Reviewers: efriedma

Reviewed By: efriedma

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D51092

llvm-svn: 340512
2018-08-23 05:18:23 +00:00
JF Bastien
c7ee4cfbef Improve incompatible triple error
When complaining that the triple is incompatible with all targets, print out the triple not just a generic error about triples not matching.

llvm-svn: 340509
2018-08-23 03:40:31 +00:00
Hsiangkai Wang
a6319a1529 [DebugInfo] Fix bug in LiveDebugVariables.
In lib/CodeGen/LiveDebugVariables.cpp, it uses std::prev(MBBI) to
get DebugValue's SlotIndex. However, the previous instruction may be
also a debug instruction. It could not use a debug instruction to query
SlotIndex in mi2iMap.

Scan all debug instructions and use the first debug instruction to query
SlotIndex for following debug instructions. Only handle DBG_VALUE in
handleDebugValue().

Differential Revision: https://reviews.llvm.org/D50621

llvm-svn: 340508
2018-08-23 03:28:24 +00:00
Scott Linder
de05e9c1b3 Fix undefined behavior in r340457
llvm-svn: 340507
2018-08-23 02:51:09 +00:00
Thomas Lively
fad152f1cd [WebAssembly] SIMD Bitwise binary arithmetic
Summary: AND, OR, and XOR. This CL depends on D51113.

Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D51136

llvm-svn: 340505
2018-08-23 00:48:37 +00:00
Thomas Lively
70a78aa9aa [WebAssembly][NFC] Reorganize SIMD instructions
Summary:
Reorganize WebAssemblyInstrSIMD.td to put all of the instruction
definitions together, making it easier to see which instructions have
been implemented already. Depends on D51143.

Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D51113

llvm-svn: 340504
2018-08-23 00:43:47 +00:00
Thomas Lively
1c41509ff7 [WebAssembly][NFC] Move specific instruction formats to specific files
Summary:
WebAssemblyInstrFormats.td retains only multiclasses that are used in
multiple other tablegen files.

Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, jfb, llvm-commits

Differential Revision: https://reviews.llvm.org/D51143

llvm-svn: 340503
2018-08-23 00:36:43 +00:00
Peter Collingbourne
2ef365f666 MC: Teach the COFF object writer to write address-significance tables.
The format is the same as in ELF: a sequence of ULEB128-encoded
symbol indexes.

Differential Revision: https://reviews.llvm.org/D51047

llvm-svn: 340499
2018-08-22 23:58:16 +00:00
Craig Topper
999526d794 [ValueTracking] Teach computeNumSignBits to understand min/max clamp patterns with constant/splat values
If we have a min/max pair we can do a better job of counting sign bits if we look at them together. This is similar to what is done in the SelectionDAG version of computeNumSignBits for ISD::SMAX/SMIN.

Differential Revision: https://reviews.llvm.org/D51112

llvm-svn: 340480
2018-08-22 23:27:50 +00:00
Craig Topper
002df6bb1f [X86] Teach combineLoopSADPattern to handle cases where there is no loop and the add has two absolute difference inputs
Previously we asumed a vector reduction add is part of a loop and one of the input is a phi. But the code in SelectionDAGBuilder that sets vector reduction flag handles more cases than that. It just requires that the use chain ends in a horizontal reduction. And there are no other uses. This means it can handle unrolled reduction loops.

If the initial value of the reduction was 0, an unrolled loop would begin with a vector reduction add that has two sad inputs. Previously we would only transform one side of the add, but for this case we need to transform both sides.

I've created a lambda to reuse some of the code for both sides. And fixed the variables names to remove reference to "phi".

Differential Revision: https://reviews.llvm.org/D50817

llvm-svn: 340478
2018-08-22 23:19:01 +00:00
Evandro Menezes
26a2cdd354 [NFC] Refactor simplification of pow()
llvm-svn: 340476
2018-08-22 23:18:02 +00:00
Thomas Lively
8e9ad7f299 [WebAssembly] Arbitrary BUILD_VECTOR and remove i64x2.mul
Summary:
This CL adds support for arbitrary BUILD_VECTORS, i.e. not splats and
not consts. This is the last feature needed to properly lower v2i64
multiplies without a i64x2.mul instruction (which is not in the spec),
so i64x2.mul is removed as well.

Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D51082

Remove unnecessary condition and fix whitespace

llvm-svn: 340472
2018-08-22 23:06:27 +00:00
Sanjay Patel
917f7adc89 [SelectionDAG] unroll unsupported vector FP ops earlier to avoid libcalls on undef elements (PR38527)
This solves the motivating case from:
https://bugs.llvm.org/show_bug.cgi?id=38527

If we are legalizing an FP vector op that maps to 1 of the LLVM intrinsics that mimic libm calls, 
but we're going to end up with scalar libcalls for that vector type anyway, then we should unroll 
the vector op into scalars before widening. This avoids libcalls because we've lost the knowledge 
that some of the scalar elements are undef.

Differential Revision: https://reviews.llvm.org/D50791

llvm-svn: 340469
2018-08-22 22:52:05 +00:00
George Burgess IV
b5e39a277d [MemorySSA] Invalidate optimized Defs upon moving them; NFC
We're currently getting this behavior implicitly, since we determine if
a Def's optimization is valid based on the ID of its defining access.
This is incorrect, though I wouldn't be surprised if this was masked in
part by that we're using a WeakVH to track what Defs are optimized to.
(Not to mention that we don't move Defs super often, AFAICT). I'll
submit a patch to fix this shortly.

This also includes a minor refactor to reduce duplication a bit.

No test is included, since like said, this already happens to be our
behavior. I'll add a test for this with my fix to the other bug
mentioned above.

llvm-svn: 340461
2018-08-22 22:34:38 +00:00
Eli Friedman
e1067659a3 [ARM] Lower llvm.ctlz.i32 to a libcall when clz is not available.
The inline sequence is very long (about 70 bytes on Thumb1), so it's
not really a good idea to inline it, especially when optimizing for
size.

Differential Revision: https://reviews.llvm.org/D47917

llvm-svn: 340458
2018-08-22 21:47:14 +00:00
Scott Linder
c46ffa9c82 [BinaryFormat] Add MessagePack reader/writer
Add support for reading and writing MessagePack, a binary object serialization
format which aims to be more compact than text formats like JSON or YAML.

The specification can be found at
https://github.com/msgpack/msgpack/blob/master/spec.md

Will be used for encoding metadata in AMDGPU code objects.

Differential Revision: https://reviews.llvm.org/D44429

llvm-svn: 340457
2018-08-22 21:42:50 +00:00
Eli Friedman
d02128f555 [SafeStack] Handle unreachable code with safe stack coloring.
Instead of asserting that the function doesn't have any unreachable
code, just ignore it for the purpose of computing liveness.

Differential Revision: https://reviews.llvm.org/D51070

llvm-svn: 340456
2018-08-22 21:38:57 +00:00
Yonghong Song
bd27c2c168 bpf: fix an assertion in BPFAsmBackend applyFixup()
Fix bug https://bugs.llvm.org/show_bug.cgi?id=38643

In BPFAsmBackend applyFixup(), there is an assertion for FixedValue to be 0.
This may not be true, esp. for optimiation level 0.
For example, in the above bug, for the following two
static variables:
  @bpf_map_lookup_elem = internal global i8* (i8*, i8*)*
      inttoptr (i64 1 to i8* (i8*, i8*)*), align 8
  @bpf_map_update_elem = internal global i32 (i8*, i8*, i8*, i64)*
      inttoptr (i64 2 to i32 (i8*, i8*, i8*, i64)*), align 8

The static variable @bpf_map_update_elem will have a symbol
offset of 8 and a FK_SecRel_8 with FixupValue 8 will cause
the assertion if llvm is built with -DLLVM_ENABLE_ASSERTIONS=ON.

The above relocations will not exist if the program is compiled
with optimization level -O1 and above as the compiler optimizes
those static variables away. In the below error message, -O2
is suggested as this is the common practice.

Note that FixedValue = 0 in applyFixup() does exist and is valid,
e.g., for the global variable my_map in the above bug. The bpf
loader will process them properly for map_id's before loading
the program into the kernel.

The static variables, which are not optimized away by compiler,
may have FK_SecRel_8 relocation with non-zero FixedValue.

The patch removed the offending assertion and will issue
a hard error as below if the FixedValue in applyFixup()
is not 0.
  $ llc -march=bpf -filetype=obj fixup.ll
  LLVM ERROR: Unsupported relocation: try to compile with -O2 or above,
      or check your static variable usage

Signed-off-by: Yonghong Song <yhs@fb.com>
llvm-svn: 340455
2018-08-22 21:21:03 +00:00
Heejin Ahn
986b1b55cb [WebAssembly] Don't write SP back when prolog is generated only for EH
Summary:
When we don't actually have stack-allocated variables but need SP only
to support EH, we don't need to write SP back in the epilog, because we
don't bump down the stack pointer.

Reviewers: dschuff

Subscribers: jgravelle-google, sbc100, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D51114

llvm-svn: 340454
2018-08-22 21:13:49 +00:00
Martin Storsjo
ace715a4e3 [ARM] Avoid injecting constant islands in movw+movt pairs on Windows
On Windows, movw+movt pairs with relocations are handled with a single
relocation that covers them both. Therefore we can't inject anything
between these instructions, otherwise the relocation (which in LLVM
only is treated as the movw instruction's relocation, while the movt
instruction's relocation is dropped) will end up bogus.

These instructions are bundled up until right before the constant
islands pass, making this effectively the only place that can split
them apart.

Differential Revision: https://reviews.llvm.org/D51032

llvm-svn: 340451
2018-08-22 20:34:12 +00:00
Martin Storsjo
f934a89e05 [ARM] Move machine operand target flags to ARMBaseInstrInfo
This makes sure the flags are available for use for thumb MIR as well.

A test that requires this will be added in the next commit.

llvm-svn: 340450
2018-08-22 20:34:06 +00:00
Krzysztof Parzyszek
a83db8d2cb [Hexagon] Enable interleaving in loop vectorizer
llvm-svn: 340447
2018-08-22 20:15:04 +00:00
Eli Friedman
c4518513f4 [ARM] Handle all-ones mask explicitly in targetShrinkDemandedConstant.
This avoids a potential infinite loop setting and unsetting bits in the
mask.

Reduced from a failure on the polly-aosp bot.

Differential Revision: https://reviews.llvm.org/D51066

llvm-svn: 340446
2018-08-22 20:13:45 +00:00
Alina Sbirlea
facf6eb783 Update MemorySSA in LoopSimplifyCFG.
Summary:
Add MemorySSA as a dependency to LoopSimplifyCFG and preserve it.
Disabled by default until all passes preserve MemorySSA.

Reviewers: bogner, chandlerc

Subscribers: sanjoy, jlebar, Prazek, george.burgess.iv, llvm-commits

Differential Revision: https://reviews.llvm.org/D50911

llvm-svn: 340445
2018-08-22 20:10:21 +00:00
Alina Sbirlea
0cb48ba57d Update MemorySSA in LoopInstSimplify.
Summary:
Add MemorySSA as a depency to LoopInstInstSimplify and preserve it.
Disabled by default until all passes preserve MemorySSA.

Reviewers: chandlerc

Subscribers: sanjoy, jlebar, Prazek, george.burgess.iv, llvm-commits

Differential Revision: https://reviews.llvm.org/D50906

llvm-svn: 340444
2018-08-22 20:05:21 +00:00
Philip Reames
eff472e2cf [AA] Remove a needless variable [NFC]
There's no need to track a seperate variable for argmemonly aliasing.  This falls out naturally of the modinfo union.  Note that we may return earlier than we would have earlier if all arguments are explicitly readnone.  The overall result doesn't change, just how we get there.

llvm-svn: 340443
2018-08-22 19:50:45 +00:00
Craig Topper
d4ada43f34 [X86] Replace (32/64 - n) shift amounts with (neg n) since the shift amount is masked in hardware
Inspired by what AArch64 does for shifts, this patch attempts to replace shift amounts with neg if we can.

This is done directly as part of isel so its as late as possible to avoid breaking some BZHI patterns since those patterns need an unmasked (32-n) to be correct.

To avoid manual load folding and custom instruction selection for the negate. I've inserted new nodes in the DAG above the shift node in topological order.

Differential Revision: https://reviews.llvm.org/D48789

llvm-svn: 340441
2018-08-22 19:39:09 +00:00
Philip Reames
d38b4efbef [AST] Minor whitespace cleanup [NFC]
llvm-svn: 340440
2018-08-22 19:30:46 +00:00
Heejin Ahn
21e1e2b060 [WebAssembly] Remove MachineFrameInfo arg from checking functions (NFC)
Summary:
There are several functions in the form of `has***` or `needs***` in
`WebAssemblyFrameLowering` and its `MachineFrameInfo` argument can be
obtained from `MachineFunction` so it is not necessarily has to be
passed from a caller. Also, it is more in line with other overriden
fuctions like `hasBP` or `hasReservedCallFrame`, which also take only
`MachineFunction` argument.

Reviewers: dschuff

Subscribers: sbc100, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D51116

llvm-svn: 340438
2018-08-22 18:53:48 +00:00
Craig Topper
60505cd1aa [X86] In OptimizeLEAs pass, check that the key is in the LEAs map before accessing
When the key is not already in the map, the access operator[] creates an empty value and grows the map.
Resizing a map is very slow, so this needs to be avoided.

Found with csmith + asserts.

May help with
https://bugs.llvm.org/show_bug.cgi?id=25843

Patch by Tom Rix.

Differential Revision: https://reviews.llvm.org/D50780

llvm-svn: 340434
2018-08-22 18:24:13 +00:00
Heejin Ahn
70e93950c8 [WebAssembly] Add hasSideEffects flag to catch instructions
Summary:
`catch` instruction certainly has rather huge side effects and the flag
was missing. At the moment this does not change any unit tests we
currently have.

Reviewers: dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D50919

llvm-svn: 340433
2018-08-22 18:22:45 +00:00
Vedant Kumar
d10dbb804e [CodeGenPrepare] Set debug locs when folding a comparison into a uadd.with.overflow
CGP can replace a branch + select with a uadd.with.overflow. Teach it to
set debug locations as it does this.

llvm-svn: 340432
2018-08-22 18:15:03 +00:00
George Burgess IV
bad97b0986 [MemorySSA] Move two simple getters; NFC
We're calling these functions quite a bit from outside of MemorySSA.cpp
now. Given that they're relatively simple one-liners, I think the style
preference is to have them inline.

llvm-svn: 340430
2018-08-22 18:02:46 +00:00
Aditya Nandakumar
436a04bdef [GISel]: Add legalization support for widening bit counting operations
https://reviews.llvm.org/D51053

Added legalization for WidenScalar of various bitcounting opcodes.

Reviewed by arsenm.

llvm-svn: 340429
2018-08-22 17:59:18 +00:00
Sam Clegg
29a6ddeafd [WebAssembly] Ensure relocation entries are ordered by offset
wasm-lld expects relocation entries to be sorted by offset.  In most
cases llvm produces them in order, but the CODE section (which combines
many MCSections) is an exception because we order the functions in
Symbol order, not in section order.  What is more, its not clear weather
`recordRelocation` is guaranteed to be called in offset order so this
sort of most likely needed in the general case too.

Differential Revision: https://reviews.llvm.org/D51065

llvm-svn: 340423
2018-08-22 17:27:31 +00:00
Samuel Pitoiset
d11ff9dda6 AMDGPU: bump AS.MAX_COMMON_ADDRESS to 6 since 32-bit addr space
32-bit constant address space is declared as 6, so the
maximum number of address spaces is 6, not 5.

Fixes "LLVM ERROR: Pointer address space out of range".

v5: rename MAX_COMMON_ADDRESS to MAX_AMDGPU_ADDRESS
v4: - fix compilation issues
    - fix out of bounds access
v3: use static_assert()
v2: add a very simple test for 32-bit addr space

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106630
llvm-svn: 340417
2018-08-22 16:08:48 +00:00
Samuel Pitoiset
a084b54d47 AMDGPU: fix existing alias rules for constant and global
Constant and global may alias, also one rules table wasn't
ordered correctly.

Pinpointed by Matt.

v2: add a test with swapped parameters
llvm-svn: 340416
2018-08-22 16:08:43 +00:00
Simon Pilgrim
a188ef13f1 [X86][SSE] LowerMULH vXi8 - use SSE shifts directly.
We know these vXi16 extended cases are legal constant splat shifts.

llvm-svn: 340414
2018-08-22 15:37:11 +00:00
Sam Parker
59400754bc [ARM] Rotated operand patterns for *xtb16
Add intrinsic isel patterns for sxtb16, sxtab16, uxtb16 and uxtab16
so that they can perform a ror.

Differential Revision: https://reviews.llvm.org/D51034

llvm-svn: 340405
2018-08-22 12:58:36 +00:00
David Green
61ff754920 [AArch64] Add Tiny Code Model for AArch64
This adds the plumbing for the Tiny code model for the AArch64 backend. This,
instead of loading addresses through the normal ADRP;ADD pair used in the Small
model, uses a single ADR. The 21 bit range of an ADR means that the code and
its statically defined symbols need to be within 1MB of each other.

This makes it mostly interesting for embedded applications where we want to fit
as much as we can in as small a space as possible.

Differential Revision: https://reviews.llvm.org/D49673

llvm-svn: 340397
2018-08-22 11:31:39 +00:00