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Commit Graph

190150 Commits

Author SHA1 Message Date
Awanish Pandey
385e6ab82f [DWARF5][DebugInfo]: Added support for DebugInfo generation for auto return type for C++ member functions.
Summary:
This patch will provide support for auto return type for the C++ member
functions. Before this return type of the member function is deduced and
stored in the DIE.
This patch includes llvm side implementation of this feature.

Patch by: Awanish Pandey <Awanish.Pandey@amd.com>

Reviewers: dblaikie, aprantl, shafik, alok, SouraVX, jini.susan.george

Reviewed by: dblaikie

Differential Revision: https://reviews.llvm.org/D70524
2020-01-13 12:26:13 +05:30
Craig Topper
20ba23ae6a [X86] Use SDNPOptInGlue instead of SDNPInGlue on a couple SDNodes.
At least one of these is used without a Glue. This doesn't seem
to change the X86GenDAGISel.inc output so maybe it doesn't matter?
2020-01-12 21:11:18 -08:00
Matt Arsenault
6c67abdba0 AMDGPU: Split test function
This avoids slightly different scheduling/regalloc behavior, and
avoids a test diff between GlobalISel and SelectionDAG.
2020-01-12 22:44:51 -05:00
Matt Arsenault
bab10482dd AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs
We don't use the xexec register classes for arbitrary values
anymore. Avoids a test variance beween GlobalISel and SelectionDAG>
2020-01-12 22:44:51 -05:00
Matt Arsenault
3a13f0680f AMDGPU/GlobalISel: Copy type when inserting readfirstlane
getDefIgnoringCopies will fail to find any def if no type is set if we
try to use it on the use's operand, so propagate the type.
2020-01-12 22:44:51 -05:00
Zheng Chen
d8d9e920a8 [SCEV] accurate range for addrecexpr with nuw flag
If addrecexpr has nuw flag, the value should never be less than its
start value and start value does not required to be SCEVConstant.

Reviewed By: nikic, sanjoy

Differential Revision: https://reviews.llvm.org/D71690
2020-01-12 20:22:37 -05:00
James Clarke
9ea03cb0fe [RISCV] Check register class for AMO memory operands
Summary:
AMO memory operands use a custom parser in order to accept both (reg)
and 0(reg). However, the validation predicate used for these operands
was only checking that they were registers, and not the register class,
so non-GPRs (such as FPRs) were also accepted. Thus, fix this by making
the predicate check that they are GPRs.

Reviewers: asb, lenary

Reviewed By: asb, lenary

Subscribers: hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D72471
2020-01-13 00:50:37 +00:00
Fangrui Song
ab21470fd6 [MC][ELF] Emit a relocation if target is defined in the same section and is non-local
For a target symbol defined in the same section, currently we don't emit
a relocation if VariantKind is VK_None (with few exceptions like RISC-V
relaxation), while GNU as emits one. This causes program behavior
differences with and without -ffunction-sections, and can break intended
symbol interposition in a -shared link.

```
.globl foo
foo:
  call foo      # no relocation. On other targets, may be written as b foo, etc
  call bar      # a relocation if bar is in another section (e.g. -ffunction-sections)
  call foo@plt  # a relocation
```

Unify these cases by always emitting a relocation. If we ever want to
optimize `call foo` in -shared links, we should emit a STB_LOCAL alias
and call via the alias.

ARM/thumb2-beq-fixup.s: we now emit a relocation to global_thumb_fn as GNU as does.
X86/Inputs/align-branch-64-2.s: we now emit R_X86_64_PLT32 to foo as GNU does.

ELF/relax.s: rewrite the test as target-in-same-section.s .
We omitted relocations to `global` and now emit R_X86_64_PLT32.
Note, GNU as does not emit a relocation for `jmp global` (maybe its own
bug). Our new behavior is compatible except `jmp global`.

Reviewed By: peter.smith

Differential Revision: https://reviews.llvm.org/D72197
2020-01-12 13:46:24 -08:00
Jay Foad
e1678ae631 [AMDGPU] Add gfx8 assembler and disassembler test cases
Summary:
This adds assembler tests for cases that were previously only in the
disassembler tests, and vice versa.

Reviewers: rampitec, arsenm, nhaehnle

Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, jfb, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D72561
2020-01-12 21:12:48 +00:00
Fangrui Song
e8e76495e7 __patchable_function_entries: don't use linkage field 'unique' with -no-integrated-as
.section name, "flags"G, @type, GroupName[, linkage]

As of binutils 2.33, linkage cannot be 'unique'.  For integrated
assembler, we use both 'o' flag and 'unique' linkage to support
--gc-sections and COMDAT with lld.

https://sourceware.org/ml/binutils/2019-11/msg00266.html
2020-01-12 12:53:44 -08:00
Markus Böck
0dd9fb199a [NFC] Fix compilation of CrashRecoveryContext.cpp on mingw
Patch by Markus Böck.

Differential Revision: https://reviews.llvm.org/D72564
2020-01-12 14:43:16 -05:00
Fangrui Song
869c74a8ef [PowerPC] Delete PPCDarwinAsmPrinter and PPCMCAsmInfoDarwin
Darwin support has been removed.

Reviewed By: nemanjai

Differential Revision: https://reviews.llvm.org/D72063
2020-01-12 11:02:02 -08:00
Simon Pilgrim
4d186c4684 [MIPS] Regenerate shl/lshr shift tests 2020-01-12 14:35:34 +00:00
Simon Pilgrim
7e136db166 [AMDGPU] Regenerate shl shift tests 2020-01-12 14:34:36 +00:00
Simon Pilgrim
c5b5b336ab [X86][AVX] Use lowerShuffleAsLanePermuteAndSHUFP to lower binary v4f64 shuffles.
Only perform this if we are shuffling lower and upper lane elements across the lanes (otherwise splitting to lower xmm shuffles would be better).

This is a regression if we shuffle build_vectors due to getVectorShuffle canonicalizing 'blend of splat' build vectors, for now I've set this not to shuffle build_vector nodes at all to avoid this.
2020-01-12 12:29:41 +00:00
Simon Pilgrim
14db9ee673 [X86][AVX] lowerShuffleAsLanePermuteAndSHUFP - only set the demanded elements of the lane mask.
Fixes an cyclic dependency issue with an upcoming patch where getVectorShuffle canonicalizes masks with splat build vector sources.
2020-01-12 09:41:40 +00:00
Fangrui Song
f9acff790a [X86][Disassembler] Merge X86DisassemblerDecoder.cpp into X86Disassembler.cpp and refactor 2020-01-12 00:53:36 -08:00
Fangrui Song
acc6f07fcd [X86][Disassembler] Simplify 2020-01-12 00:53:35 -08:00
Qiu Chaofan
2824df2498 [NFC] Refactor memory ops cluster method
Current implementation of BaseMemOpsClusterMutation is a little bit
obscure. This patch directly uses a map from store chain ID to set of
memory instrs to make it simpler, so that future improvements are easier
to read, update and review.

Reviewed By: evandro

Differential Revision: https://reviews.llvm.org/D72070
2020-01-12 13:10:04 +08:00
Craig Topper
bc5c331a14 [X86] Don't call LowerSETCC from LowerSELECT for STRICT_FSETCC/STRICT_FSETCCS nodes.
This causes the STRICT_FSETCC/STRICT_FSETCCS nodes to lowered
early while lowering SELECT, but the output chain doesn't get
connected. Then we visit the node again when it is its turn
because we haven't replaced the use of the chain result. In the
case of the fp128 libcall lowering, after D72341 this will cause
the libcall to be emitted twice.
2020-01-11 20:43:00 -08:00
Zheng Chen
1c93f5af35 [SCEV] more accurate range for addrecexpr with nsw flag.
Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D72436
2020-01-11 23:26:35 -05:00
Craig Topper
0744d792d5 [LegalizeVectorOps] Parallelize the lo/hi part of STRICT_UINT_TO_FLOAT legalization.
The lo and hi computation are independent. Give them the same input
chain and TokenFactor the results together.
2020-01-11 17:50:30 -08:00
Craig Topper
18c0ac74a3 [TargetLowering][X86] Connect the chain from STRICT_FSETCC in TargetLowering::expandFP_TO_UINT and X86TargetLowering::FP_TO_INTHelper. 2020-01-11 17:50:20 -08:00
Craig Topper
19d3f5440d [LegalizeVectorOps] Expand vector MERGE_VALUES immediately.
Custom legalization can produce MERGE_VALUES to return multiple
results. We can expand them immediately instead of leaving them
around for DAG combine to clean up.
2020-01-11 17:50:20 -08:00
Fangrui Song
491409978c [X86][Disassembler] Shrink X86GenDisassemblerTables.inc from 36M to 6.1M
In x86Disassembler{OneByte,TwoByte,...}Codes,
"/* EmptyTable */" is very common. Omitting it saves lots of space.
Also, there is no need to display a table entry in multiple lines.

It is also common that the whole OpcodeDecision is { MODRM_ONEENTRY, 0}.
Make use of zero-initialization.
2020-01-11 17:28:22 -08:00
Fangrui Song
da427b145f [X86][Disassembler] Optimize argument passing and immediate reading 2020-01-11 15:43:26 -08:00
Fangrui Song
3a9f350cbb [Disassembler] Delete the VStream parameter of MCDisassembler::getInstruction()
The argument is llvm::null() everywhere except llvm::errs() in
llvm-objdump in -DLLVM_ENABLE_ASSERTIONS=On builds. It is used by no
target but X86 in -DLLVM_ENABLE_ASSERTIONS=On builds.

If we ever have the needs to add verbose log to disassemblers, we can
record log with a member function, instead of passing it around as an
argument.
2020-01-11 13:34:52 -08:00
Lang Hames
6d930a5412 [ORC] Fix argv handling in runAsMain / lli.
This fixes an off-by-one error in the argc value computed by runAsMain, and
switches lli back to using the input bitcode (rather than the string "lli") as
the effective program name.

Thanks to Stefan Graenitz for spotting the bug.
2020-01-11 13:03:38 -08:00
Alexandre Ganea
5331eb3b9c [Support] Optionally call signal handlers when a function wrapped by the the CrashRecoveryContext fails
This patch allows for handling a failure inside a CrashRecoveryContext in the same way as the global exception/signal handler. A failure will have the same side-effect, such as cleanup of temporarty file, printing callstack, calling relevant signal handlers, and finally returning an exception code. This is an optional feature, disabled by default.
This is a support patch for D69825.

Differential Revision: https://reviews.llvm.org/D70568
2020-01-11 15:27:07 -05:00
Fangrui Song
f973ddb04b [X86][Disassembler] Replace custom logger with LLVM_DEBUG
llvm-objdump -d on clang is decreased from 7.8s to 7.4s.

The improvement is likely due to the elimination of logger setup and
dbgprintf(), which has a large overhead.
2020-01-11 12:17:05 -08:00
Craig Topper
5d8bb888c1 [LegalizeVectorOps] Remove some of the simpler Expand methods. Pass Results vector to a couple. NFCI
Some of the simplest handlers just call TLI and if that fails,
they fall back to unrolling. For those just inline the TLI call
and share the unrolling call with the default case of Expand.

For ExpandFSUB and ExpandBITREVERSE so that its obvious they
don't return results sometimes and want to defer to LegalizeDAG.
2020-01-11 12:14:19 -08:00
Craig Topper
5d5ab3d281 [LegalizeVectorOps] Only pass SDNode* instead SDValue to all of the Expand* and Promote* methods.
All the Expand* and Promote* function assume they are being
called with result 0 anyway. Just hardcode result 0 into them.
2020-01-11 11:41:23 -08:00
Fangrui Song
5e7f810e7d [X86][Disassembler] Simplify and optimize reader functions
llvm-objdump -d on clang is decreased from 8.2s to 7.8s.
2020-01-11 11:24:38 -08:00
Craig Topper
dccc4683f8 [X86] Turn FP_ROUND/STRICT_FP_ROUND into X86ISD::VFPROUND/STRICT_VFPROUND during PreprocessISelDAG to remove some duplicate isel patterns. 2020-01-11 11:06:52 -08:00
Lang Hames
92479bab85 [ExecutionEngine] Re-enable FastISel for non-iOS arm targets.
Patch by Nicolas Capens. Thanks Nicolas!

https://reviews.llvm.org/D65015
2020-01-11 10:49:59 -08:00
Philip Reames
01cf1a3805 [X86] Adjust nop emission by compiler to consider target decode limitations
The primary motivation of this change is to bring the code more closely in sync behavior wise with the assembler's version of nop emission.  I'd like to eventually factor them into one, but that's hard to do when one has features the other doesn't.

The longest encodeable nop on x86 is 15 bytes, but many processors - for instance all intel chips - can't decode the 15 byte form efficiently.  On those processors, it's better to use either a 10 byte or 11 byte sequence depending.
2020-01-11 08:45:17 -08:00
Philip Reames
d59f41ce54 [X86AsmBackend] Move static function before sole use [NFC] 2020-01-11 08:45:17 -08:00
Philip Reames
c8d30c065e [X86AsmBackend] Be consistent about placing definitions out of line [NFC] 2020-01-11 08:45:17 -08:00
Simon Pilgrim
30fec04253 Fix uninitialized value clang static analyzer warning. NFC. 2020-01-11 16:02:22 +00:00
Simon Pilgrim
07757bd26d moveOperands - assert Src/Dst MachineOperands are non-null.
Fixes static-analyzer warnings.
2020-01-11 14:37:19 +00:00
Simon Pilgrim
98153c77dd [X86] Fix outdated comment
The generic saturated math opcodes are no longer widened inside X86TargetLowering
2020-01-11 14:37:18 +00:00
Simon Pilgrim
c623e10ed2 Fix copy+paste typo in shuffle test name 2020-01-11 12:42:01 +00:00
Simon Pilgrim
3295916d10 [X86][AVX] Add lowerShuffleAsLanePermuteAndSHUFP lowering
Add initial support for lowering v4f64 shuffles to SHUFPD(VPERM2F128(V1, V2), VPERM2F128(V1, V2)), eventually this could be used for v8f32 (and maybe v8f64/v16f32) but I'm being conservative for the initial implementation as only v4f64 can always succeed.

This currently is only called from lowerShuffleAsLanePermuteAndShuffle so only gets used for unary shuffles, and we limit this to cases where we use upper elements as otherwise concating 2 xmm shuffles is probably the better case.

Helps with poor shuffles mentioned in D66004.
2020-01-11 12:42:00 +00:00
Florian Hahn
f4d29d71b3 [X86] Add more complex tests for vector masks used with AND/OR/XOR.
Additional test cases for D72524.
2020-01-11 12:13:10 +00:00
Nuno Lopes
e59e19e267 DSE: fix bug where we would only check libcalls for name rather than whole decl 2020-01-11 11:57:29 +00:00
Nikita Popov
9a6b5ddc4c [LoopRotate] Add tests for rotate with switch; NFC
For D72420.
2020-01-11 11:03:29 +01:00
Nikita Popov
273d3ef7cc [LoopSimplify] Regenerate test checks; NFC
For D72519.
2020-01-11 11:02:24 +01:00
Nikita Popov
ec2a6f1b2d [InstCombine] Preserve nuw on sub of geps (PR44419)
Fix https://bugs.llvm.org/show_bug.cgi?id=44419 by preserving the
nuw on sub of geps. We only do this if the offset has a multiplication
as the final operation, as we can't be sure the operations is nuw
in the other cases without more thorough analysis.

Differential Revision: https://reviews.llvm.org/D72048
2020-01-11 11:01:12 +01:00
Craig Topper
516dc2411b [X86] Remove dead code from X86DAGToDAGISel::Select that is no longer needed now that we don't mutate strict fp nodes. NFC 2020-01-11 00:27:14 -08:00
Craig Topper
0f4bc22841 [X86] Simplify code by removing an unreachable condition. NFCI
For X87<->SSE conversions, the SSE type is always smaller than
the X87 type. So we can always use the smallest type for the
memory type.
2020-01-10 23:41:06 -08:00