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11295 Commits

Author SHA1 Message Date
Andrew Trick
e77cdffcf3 The ARM jit cannot handle these tests as of 2010-10-27. 
(A PR will be linked to this rev.)

llvm-svn: 117620
 2010-10-29 00:23:43 +00:00
Rafael Espindola
913ce7ebc8 Improvements to .section parsing: 
* If we have a M or a G, reject sections without the type
* Only parse the flag specific arguments if we have M or G
* Parse the corresponding arguments for M and G

We ignore the G arguments and flag for now.

llvm-svn: 117608
 2010-10-28 21:33:33 +00:00
Chris Lattner
1917294eb5 most simple arm instructions match correctly now, 
it looks like we're not handling [] operands though

llvm-svn: 117607
 2010-10-28 21:31:07 +00:00
Chris Lattner
bd838d16e5 fix the asmmatcher generator to handle targets with no RegisterPrefix 
(like ARM) correctly.  With this change, we can now match "bx lr"
because we recognize lr as a register.

llvm-svn: 117606
 2010-10-28 21:28:42 +00:00
Rafael Espindola
b562975139 Add support for the .string directive. 
llvm-svn: 117592
 2010-10-28 20:02:27 +00:00
Rafael Espindola
f230319275 Defined weak symbols should have non-zero value. 
llvm-svn: 117585
 2010-10-28 19:39:57 +00:00
Rafael Espindola
862d688cbd Fix relocations with renamed symbols. 
llvm-svn: 117575
 2010-10-28 19:08:03 +00:00
Rafael Espindola
e62cf892ae Aliases defined with .symver should copy the binding of the symbols they alias. 
Move the existing patching for undefined symbols so that all the patching
is done in the same function.

llvm-svn: 117570
 2010-10-28 18:33:03 +00:00
Bob Wilson
65124cd7c7 Teach the DAG combiner to fold a splat of a splat. Radar 8597790. 
Also do some minor refactoring to reduce indentation.

llvm-svn: 117558
 2010-10-28 17:06:14 +00:00
Roman Divacky
8555f153e9 Implement .equ directive as a synonym to .set. 
llvm-svn: 117553
 2010-10-28 16:22:58 +00:00
Duncan Sands
60f016b0f9 Testcase for PR8494 (invalid bitcode crashing the bitcode reader). 
llvm-svn: 117552
 2010-10-28 15:57:30 +00:00
Rafael Espindola
ff7e4e4e43 Implement R_X86_64_DTPOFF32. 
llvm-svn: 117548
 2010-10-28 15:11:03 +00:00
Rafael Espindola
1d1ff5485c Implement TLSLD. 
llvm-svn: 117547
 2010-10-28 15:02:40 +00:00
Rafael Espindola
8372247e83 Implement DTPOFF. 
llvm-svn: 117546
 2010-10-28 14:48:59 +00:00
Rafael Espindola
c44c5b374a Implement TLSLDM. 
llvm-svn: 117544
 2010-10-28 14:37:09 +00:00
Rafael Espindola
d8ef67f8b9 Implement VK_GOTNTPOFF and switch RelocNeedsGOT to use VariantKind. 
llvm-svn: 117543
 2010-10-28 14:22:44 +00:00
Evan Cheng
bc4588c439 Re-commit 117518 and 117519 now that ARM MC test failures are out of the way. 
llvm-svn: 117531
 2010-10-28 06:47:08 +00:00
Evan Cheng
72be097417 Disable most of the ARM vfp / NEON MC tests. These are too fragile to be useful. 
I'll work with Jim, Owen, and Bill on an alternative testing strategy until
the assembly parser is available.

llvm-svn: 117530
 2010-10-28 06:46:17 +00:00
NAKAMURA Takumi
b89aaebdde test/Transforms/SimplifyLibCalls/floor.ll: Mark as XFAIL:win32 due to lack of nearbyintf on MSVC. [PR8466] 
llvm-svn: 117529
 2010-10-28 06:46:04 +00:00
Evan Cheng
fdc80a0316 Revert 117518 and 117519 for now. They changed scheduling and cause MC tests to fail. Ugh. 
llvm-svn: 117520
 2010-10-28 02:00:25 +00:00
Evan Cheng
5c358e02ea - Assign load / store with shifter op address modes the right itinerary classes. 
- For now, loads of [r, r] addressing mode is the same as the
  [r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
  identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
  is "free".

llvm-svn: 117519
 2010-10-28 01:49:06 +00:00
Dale Johannesen
b78530f9b0 Fix pastos in handling of AVX cvttsd2si, PR8491. 
Bruno, please review, but I'm pretty sure this is right.
Patch by Alex Mac!

llvm-svn: 117514
 2010-10-28 00:35:54 +00:00
Owen Anderson
e75f7c5419 Add correct NEON encodings for vtbl and vtbx. 
llvm-svn: 117513
 2010-10-28 00:18:46 +00:00
Owen Anderson
008116cb71 Add correct NEON encodings for vext, vtrn, vuzp, and vzip. 
llvm-svn: 117512
 2010-10-27 23:56:39 +00:00
Dale Johannesen
454b9243bd Teach InstCombine not to use Add and Neg on FP. PR 8490. 
llvm-svn: 117510
 2010-10-27 23:45:18 +00:00
Evan Cheng
44d2802e1d Shifter ops are not always free. Do not fold them (especially to form 
complex load / store addressing mode) when they have higher cost and
when they have more than one use.

llvm-svn: 117509
 2010-10-27 23:41:30 +00:00
Owen Anderson
27049dbce3 Tests for NEON encoding of vrev. 
llvm-svn: 117502
 2010-10-27 22:54:49 +00:00
Owen Anderson
9437a20a72 Provide correct encodings for NEON vcvt, which has its own special immediate encoding 
for specifying fractional bits for fixed point conversions.

llvm-svn: 117501
 2010-10-27 22:49:00 +00:00
Owen Anderson
d28d229ded Provide correct encodings for the get_lane and set_lane variants of vmov. 
llvm-svn: 117495
 2010-10-27 21:28:09 +00:00
Rafael Espindola
68ec803155 Add support for R_386_TLS_GD, R_386_TLS_LE_32, R_386_TLS_IE and R_386_TLS_LE. 
llvm-svn: 117494
 2010-10-27 21:23:52 +00:00
Kevin Enderby
a53cc6a764 Added the x86 instruction ud2b (2nd official undefined instruction). 
llvm-svn: 117485
 2010-10-27 20:46:49 +00:00
Bob Wilson
cdc8dff3ac SelectionDAG shuffle nodes do not allow operands with different numbers of 
elements than the result vector type.  So, when an instruction like:

%8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2>

is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements.  That is:

shuffle [a,b], [c,d] is changed to:
shuffle [a,b,u,u], [c,d,u,u]

That's probably the right thing for x86 but for NEON, we'd much rather have:

shuffle [a,b,c,d], undef

Teach the DAG combiner how to do that transformation for ARM.  Radar 8597007.

llvm-svn: 117482
 2010-10-27 20:38:28 +00:00
Rafael Espindola
2ea1239070 Implement R_X86_64_GOTTPOFF, R_X86_64_TLSGD and R_X86_64_TPOFF32. 
llvm-svn: 117481
 2010-10-27 20:28:07 +00:00
Owen Anderson
7c46fcfee4 Provide correct NEON encodings for vdup. 
llvm-svn: 117475
 2010-10-27 19:25:54 +00:00
Rafael Espindola
4db628cd34 Set default type and flags for .init and .fini. 
llvm-svn: 117471
 2010-10-27 18:45:20 +00:00
Owen Anderson
dbed42aff5 Tests for NEON encoding of vmovl, vmovn, vqmovn, and vqmovun. 
llvm-svn: 117469
 2010-10-27 18:17:12 +00:00
Owen Anderson
25d75e80ba Tests for NEON encoding of vcls, vclz, and vcnt. 
llvm-svn: 117466
 2010-10-27 18:05:25 +00:00
Owen Anderson
a5643da004 Tests for NEON encoding of vneg and vqneg. 
llvm-svn: 117463
 2010-10-27 17:57:26 +00:00
Rafael Espindola
ca302c994a Produce an error for an invalid use of .symver. 
llvm-svn: 117462
 2010-10-27 17:56:18 +00:00
Owen Anderson
32da0e6e3f Tests for NEON encoding of vabs and vqabs. 
llvm-svn: 117460
 2010-10-27 17:50:07 +00:00
Owen Anderson
c8757eb137 Add correct NEON encodings for vsli and vsri. 
llvm-svn: 117459
 2010-10-27 17:40:08 +00:00
Owen Anderson
e64b7187a9 Add correct NEON encodings for vsra and vrsra. 
llvm-svn: 117458
 2010-10-27 17:29:29 +00:00
Rafael Espindola
58a0ea80a4 Symbols defined as the difference of other two end up in the ABS section. 
llvm-svn: 117451
 2010-10-27 16:04:30 +00:00
Rafael Espindola
23d05a8675 Add support for the .symver directive. This is really ugly, but most of it is 
contained in the ELF object writer.

llvm-svn: 117448
 2010-10-27 15:18:17 +00:00
Kevin Enderby
74a2614673 Yet another tweak to X86 instructions to add ud2a as an alias to ud2 
(still to add ud2b).

llvm-svn: 117435
 2010-10-27 03:01:02 +00:00
Kevin Enderby
d22f3b9de7 Another tweak to X86 instructions to add the missing flex instruction (without 
the wait prefix).

llvm-svn: 117434
 2010-10-27 02:53:04 +00:00
Kevin Enderby
e812b356cc Tweaks to X86 instructions to allow the 'w' suffix in places it makes 
sense, when the instruction takes the 16-bit ax register or m16 memory
location.  These changes to llvm-mc matches what the darwin assembler
allows for these instructions.  Done differently than in r117031 that
caused a valgrind error which was later reverted.

llvm-svn: 117433
 2010-10-27 02:32:19 +00:00
Kevin Enderby
d5235bb45c Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc 
will accept versions that the darwin assembler allows.  Forms ending in "pi" and
forms without all the operands.

llvm-svn: 117427
 2010-10-27 00:59:28 +00:00
Owen Anderson
1dc05f20e2 Add correct NEON encodings for vqshl, vqshrn, vqshrun, vqrshl, vqshrn, and vqrshrun. 
llvm-svn: 117411
 2010-10-26 22:50:46 +00:00
Owen Anderson
55c0bad37d Correct NEON encodings for vshrn, vrshl, vrshr, vrshrn. 
llvm-svn: 117402
 2010-10-26 21:58:41 +00:00