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Author SHA1 Message Date
Jakob Stoklund Olesen
05823401a6 Use precomputed BitVector for CodeGenRegisterClass::hasSubClass(). 
All the sub-class bit vectors are computed when first creating the
register bank.

llvm-svn: 140905
 2011-09-30 23:47:05 +00:00
Bill Wendling
98db234c02 Filecheck-ize. 
llvm-svn: 140904
 2011-09-30 23:40:29 +00:00
Bill Wendling
252b649025 Add new line at end of file. 
llvm-svn: 140903
 2011-09-30 23:21:11 +00:00
Bill Wendling
fcf3096d9b When inferring the pointer alignment, if the global doesn't have an initializer 
and the alignment is 0 (i.e., it's defined globally in one file and declared in
another file) it could get an alignment which is larger than the ABI allows for
that type, resulting in aligned moves being used for unaligned loads.

For instance, in file A.c:

   struct S s;

In file B.c:
   struct {
     // something long
   };
   extern S s;

   void foo() {
     struct S p = s;
     // ...
   }

this copy is a 'memcpy' which is turned into a series of 'movaps' instructions
on X86. But this is wrong, because 'struct S' has alignment of 4, not 16.

llvm-svn: 140902
 2011-09-30 23:19:55 +00:00
Nick Lewycky
598be18371 Promote comment to doxycomment. Adjust whitespace. No functionality change. 
llvm-svn: 140899
 2011-09-30 22:19:53 +00:00
Jakob Stoklund Olesen
010e9bb778 Store sub-class lists as a bit vector. 
This uses less memory and it reduces the complexity of sub-class
operations:

- hasSubClassEq() and friends become O(1) instead of O(N).

- getCommonSubClass() becomes O(N) instead of O(N^2).

In the future, TableGen will infer register classes.  This makes it
cheap to add them.

llvm-svn: 140898
 2011-09-30 22:19:07 +00:00
Jakob Stoklund Olesen
4c57e66252 Extract a slightly more general BitVector printer. 
This one can also print 32-bit groups.

llvm-svn: 140897
 2011-09-30 22:18:54 +00:00
Jakob Stoklund Olesen
b0b79fa82c Move getCommonSubClass() into TRI. 
It will soon need the context.

llvm-svn: 140896
 2011-09-30 22:18:51 +00:00
Jakob Stoklund Olesen
402aa89d8a Compute lists of super-classes in CodeGenRegisterClass. 
Use these lists instead of computing them on the fly in
RegisterInfoEmitter.

llvm-svn: 140895
 2011-09-30 22:18:45 +00:00
Jim Grosbach
355190250f Correct for my over-eager delete finger. 
llvm-svn: 140892
 2011-09-30 22:02:45 +00:00
Akira Hatanaka
067f6ce2f1 Add definition of MipsELFObjectWriter. 
Patch by Reed Kotler at Mips Technologies.

llvm-svn: 140891
 2011-09-30 21:55:40 +00:00
Akira Hatanaka
13aa92d8c2 Register the MC object streamer. 
Patch by Reed Kotler at Mips Technologies.

llvm-svn: 140887
 2011-09-30 21:29:38 +00:00
Akira Hatanaka
3048f0ddf4 Register Asm backend. Add functions to MipsAsmBackend. 
Patch by Reed Kotler at Mips Technologies.

llvm-svn: 140886
 2011-09-30 21:23:45 +00:00
Akira Hatanaka
f1c17f8e83 Add MCELFObjectTargetWriter and MCAsmBackend classes. 
Patch by Reed Kotler at Mips Technologies.

llvm-svn: 140885
 2011-09-30 21:04:02 +00:00
David Greene
7a9ac03042 Test More Complicated Lists 
Test of indexing lists of lists of lists works.  This also exercises
some operators.

llvm-svn: 140884
 2011-09-30 20:59:52 +00:00
David Greene
c5830e015f Test VarListElementInit:: resolveListElementReference 
Add a TableGen test to check if indexing lists of lists works.

llvm-svn: 140883
 2011-09-30 20:59:51 +00:00
David Greene
2d3533a153 Implement VarListElementInit:: resolveListElementReference 
Implement VarListElementInit:: resolveListElementReference so that
lists of lists can be indexed.

llvm-svn: 140882
 2011-09-30 20:59:49 +00:00
Benjamin Kramer
004c20ec00 Update CMake build. 
llvm-svn: 140879
 2011-09-30 20:44:33 +00:00
Akira Hatanaka
9f9e71147e Initial implementation of MipsMCCodeEmitter. 
Patch by Reed Kotler at Mips Technologies.

llvm-svn: 140878
 2011-09-30 20:40:03 +00:00
Jim Grosbach
96af96b83d Don't modify constant in-place. 
llvm-svn: 140875
 2011-09-30 19:58:46 +00:00
Andrew Trick
e6f65d16d1 Tracing or debug-printing a newly formed instruction should not crash. 
llvm-svn: 140874
 2011-09-30 19:50:40 +00:00
Andrew Trick
6f589802f8 whitespace 
llvm-svn: 140873
 2011-09-30 19:48:58 +00:00
Akira Hatanaka
5479850400 Remove unnecessary checking of register operands. 
llvm-svn: 140872
 2011-09-30 19:18:24 +00:00
Akira Hatanaka
c9268767d6 Add definitions of Mips64 rotate instructions. 
llvm-svn: 140870
 2011-09-30 18:51:46 +00:00
Jim Grosbach
d35eaaeb6e float comparison to double 'zero' constant can just be a float 'zero.' 
InstCombine was incorrectly considering the conversion of the constant
zero to be unsafe.

We want to transform:
define float @bar(float %x) nounwind readnone optsize ssp {
  %conv = fpext float %x to double
  %cmp = fcmp olt double %conv, 0.000000e+00
  %conv1 = zext i1 %cmp to i32
  %conv2 = sitofp i32 %conv1 to float
  ret float %conv2
}

Into:
define float @bar(float %x) nounwind readnone optsize ssp {
  %cmp = fcmp olt float %x, 0.000000e+00   ; <---- This
  %conv1 = zext i1 %cmp to i32
  %conv2 = sitofp i32 %conv1 to float
  ret float %conv2
}


rdar://10215914

llvm-svn: 140869
 2011-09-30 18:45:50 +00:00
Bill Wendling
1485fec8b1 Constify 'isLSDA' and move a method out-of-line. 
llvm-svn: 140868
 2011-09-30 18:42:06 +00:00
Jim Grosbach
651c847dc5 Tidy up. Trailing whitespace. 
llvm-svn: 140865
 2011-09-30 18:09:53 +00:00
Jim Grosbach
44047da675 ARM Darwin default relocation model is PIC. 
This matches clang, so default options in llc and friends are now closer to
clang's defaults.

llvm-svn: 140863
 2011-09-30 17:41:35 +00:00
Akira Hatanaka
6f3cfcdb95 isCommutable should be 0 for DSUBu. 
llvm-svn: 140862
 2011-09-30 17:26:36 +00:00
Jim Grosbach
5b31ef50f5 ARM Fixup valus for movt/movw are for the whole value. 
Remove an assert that was expecting only the relevant 16bit portion for
the fixup being handled. Also kill some dead code in the T2 portion.

rdar://9653509

llvm-svn: 140861
 2011-09-30 17:23:05 +00:00
Akira Hatanaka
ffa28d49f1 Check values of immediate operands. 
llvm-svn: 140860
 2011-09-30 17:19:21 +00:00
Jakob Stoklund Olesen
783b18e818 Fix a bug in compare_numeric(). 
Thanks to Alexandru Dura and Jonas Paulsson for finding it.

llvm-svn: 140859
 2011-09-30 17:03:55 +00:00
Duncan Sands
14b9c222c6 Add forgotten tests that the cleanup flag is cleared if there 
is a catch-all landingpad clause.

llvm-svn: 140858
 2011-09-30 17:00:34 +00:00
Danil Malyshev
73aeedab45 MCJIT initialization TargetData 
llvm-svn: 140856
 2011-09-30 16:40:10 +00:00
Justin Holewinski
f088db2687 PTX: Various stylistic and code readability changes recommended by Jim Grosbach. 
llvm-svn: 140855
 2011-09-30 14:36:36 +00:00
Justin Holewinski
2a5786383a PTX: Add programmable rounding mode specifier for int <-> fp conversion instrs. 
Also take this opportunity to clean up the rounding mode pass.

llvm-svn: 140854
 2011-09-30 13:46:52 +00:00
Duncan Sands
b4c8b2d9fa Inlining often produces landingpad instructions with repeated 
catch or repeated filter clauses.  Teach instcombine a bunch
of tricks for simplifying landingpad clauses.  Currently the
code only recognizes the GNU C++ and Ada personality functions,
but that doesn't stop it doing a bunch of "generic" transforms
which are hopefully fine for any real-world personality function.
If these "generic" transforms turn out not to be generic, they
can always be conditioned on the personality function.  Probably
someone should add the ObjC++ personality function.  I didn't as
I don't know anything about it.

llvm-svn: 140852
 2011-09-30 13:12:16 +00:00
Torok Edwin
774d60816b some 3.0 API notes 
llvm-svn: 140851
 2011-09-30 13:07:52 +00:00
Torok Edwin
5df4e64d7b Comment grammar fixes. 
thanks to Duncan.

llvm-svn: 140850
 2011-09-30 13:07:47 +00:00
Justin Holewinski
f86bf451e4 PTX: Attempt to cleanup/unify the handling of FP rounding modes. This requires 
us to manually provide Pat<> definitions for all FP instruction patterns.

llvm-svn: 140849
 2011-09-30 12:54:43 +00:00
Torok Edwin
10dcb27bb4 Instead of crashing when MCAsmInfo is NULL, add an assert. 
This helps with porting code from 2.9 to 3.0 as TargetSelect.h changed location,
and if you include the old one by accident you will trigger this assert.

llvm-svn: 140848
 2011-09-30 12:31:57 +00:00
Akira Hatanaka
dcd69c2e07 Mips64 shift instructions. 
llvm-svn: 140841
 2011-09-30 03:18:46 +00:00
Akira Hatanaka
4bdb4b1958 Mips64 arithmetic and logical instructions with one source register and 
immediate.

llvm-svn: 140839
 2011-09-30 02:08:54 +00:00
Jim Grosbach
d94ffffc87 ARM fix encoding of VMOV.f32 and VMOV.f64 immediates. 
Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.

rdar://10211428

llvm-svn: 140834
 2011-09-30 00:50:06 +00:00
Jakob Stoklund Olesen
82a55057c4 Precompute a bit vector of register sub-classes. 
llvm-svn: 140827
 2011-09-30 00:10:40 +00:00
Jakob Stoklund Olesen
35c649f61b Order register classes topologically. 
All register classes are given a lower ID than their sub-classes.
Cliques are ordered alphabetically.

This will be used to simplify some sub-class operations.

llvm-svn: 140826
 2011-09-30 00:10:36 +00:00
Akira Hatanaka
50a4f6d570 Fill delay slot with useful instructions. Modified from Sparc's version of delay 
slot filler.

Patch by Reed Kotler at Mips Technologies.

llvm-svn: 140825
 2011-09-29 23:52:13 +00:00
Bill Wendling
ee48218f94 Create a machine basic block in the constant pool and retrieve the symbol for an MBB. 
llvm-svn: 140824
 2011-09-29 23:50:42 +00:00
Bill Wendling
de36760902 Support creating a constant pool value for a machine basic block. 
This is used when we want to take the address of a machine basic block, but it's
not associated with a BB in LLVM IR.

llvm-svn: 140823
 2011-09-29 23:48:44 +00:00
Nick Lewycky
fc476a3d3f Fold two identical set lookups into one. No functionality change. 
llvm-svn: 140821
 2011-09-29 23:40:12 +00:00