Johnny Chen
e88573849d
There were two issues fixed:
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1. The ARM Darwin *r9 call instructions were pseudo-ized recently.
Modify the ARMDisassemblerCore.cpp file to accomodate the change.
2. The disassembler was unnecessarily adding 8 to the sign-extended imm24:
imm32 = SignExtend(imm24:'00', 32); // A8.6.23 BL, BLX (immediate)
// Encoding A1
It has no business doing such. Removed the offending logic.
Add test cases to arm-tests.txt.
llvm-svn: 127707
2011-03-15 22:27:33 +00:00
Bill Wendling
c12aadb9b6
The VTBL (and VTBX) instructions are rather permissive concerning the masks they
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accept. If a value in the mask is out of range, it uses the value 0, for VTBL,
or leaves the value unchanged, for VTBX.
llvm-svn: 127700
2011-03-15 21:15:20 +00:00
Bill Wendling
388dad6d62
Some minor cleanups based on feedback.
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llvm-svn: 127694
2011-03-15 20:47:26 +00:00
Evan Cheng
59ba6777c3
Do not form thumb2 ldrd / strd if the offset is by multiple of 4. rdar://9133587
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llvm-svn: 127683
2011-03-15 18:41:52 +00:00
Johnny Chen
a86399b8e6
Fixed an ARM disassembler bug where it does not handle STRi12 correctly because an extra
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register operand was erroneously added. Remove an incorrect assert which triggers the bug.
rdar://problem/9131529
llvm-svn: 127642
2011-03-15 01:13:17 +00:00
Jim Grosbach
3de97c6e32
Clean up ARM tail calls a bit. They're pseudo-instructions for normal branches.
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Also more cleanly separate the ARM vs. Thumb functionality. Previously, the
encoding would be incorrect for some Thumb instructions (the indirect calls).
llvm-svn: 127637
2011-03-15 00:30:40 +00:00
Bill Wendling
da1364d669
Generate a VTBL instruction instead of a series of loads and stores when we
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can. As Nate pointed out, VTBL isn't super performant, but it *has* to be better
than this:
_shuf:
@ BB#0: @ %entry
push {r4, r7, lr}
add r7, sp, #4
sub sp, #12
mov r4, sp
bic r4, r4, #7
mov sp, r4
mov r2, sp
vmov d16, r0, r1
orr r0, r2, #6
orr r3, r2, #7
vst1.8 {d16[0]}, [r3]
vst1.8 {d16[5]}, [r0]
subs r4, r7, #4
orr r0, r2, #5
vst1.8 {d16[4]}, [r0]
orr r0, r2, #4
vst1.8 {d16[4]}, [r0]
orr r0, r2, #3
vst1.8 {d16[0]}, [r0]
orr r0, r2, #2
vst1.8 {d16[2]}, [r0]
orr r0, r2, #1
vst1.8 {d16[1]}, [r0]
vst1.8 {d16[3]}, [r2]
vldr.64 d16, [sp]
vmov r0, r1, d16
mov sp, r4
pop {r4, r7, pc}
The "illegal" testcase in vext.ll is no longer illegal.
<rdar://problem/9078775>
llvm-svn: 127630
2011-03-14 23:02:38 +00:00
Jim Grosbach
6ee5aef028
Remove some dead patterns.
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llvm-svn: 127601
2011-03-14 18:34:35 +00:00
Evan Cheng
fbb846289a
Indentation.
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llvm-svn: 127595
2011-03-14 18:02:30 +00:00
Eric Christopher
80a45901e0
Sometimes isPredicable lies to us and tells us we don't need the operands.
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Go ahead and add them on when we might want to use them and let
later passes remove them.
Fixes rdar://9118569
llvm-svn: 127518
2011-03-12 01:09:29 +00:00
Jim Grosbach
f7531e7697
Add FIXME.
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llvm-svn: 127516
2011-03-12 00:51:00 +00:00
Jim Grosbach
555d910477
Pseudo-ize the ARM Darwin *r9 call instruction definitions. They're the same
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actual instruction as the non-Darwin defs, but have different call-clobber
semantics and so need separate patterns. They don't need to duplicate the
encoding information, however.
llvm-svn: 127515
2011-03-12 00:45:26 +00:00
Jim Grosbach
923c731f15
Add a FIXME.
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llvm-svn: 127511
2011-03-11 23:25:21 +00:00
Jim Grosbach
daffeb06fb
Pseudo-ize the ARM 'B' instruction.
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llvm-svn: 127510
2011-03-11 23:24:15 +00:00
Jim Grosbach
2226dfbea2
Remove dead code. These ARM instruction definitions no longer exist.
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llvm-svn: 127509
2011-03-11 23:15:02 +00:00
Jim Grosbach
009af69d6d
Pseudo-ize VMOVDcc and VMOVScc.
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llvm-svn: 127506
2011-03-11 23:09:50 +00:00
Jim Grosbach
61ff87cd2d
80 columns
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llvm-svn: 127505
2011-03-11 23:00:16 +00:00
Jim Grosbach
27eaca3e0d
Properly pseudo-ize the ARM LDMIA_RET instruction. This has the nice side-
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effect that we get proper instruction printing using the "pop" mnemonic for it.
llvm-svn: 127502
2011-03-11 22:51:41 +00:00
Jim Grosbach
ee6075cda5
ARM VDUPfd and VDUPfq can just be patterns. The instruction is the same
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as for VDUP32d and VDUP32q, respectively.
llvm-svn: 127489
2011-03-11 20:44:08 +00:00
Jim Grosbach
3329263352
ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32q
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and VDUPLN32d, respectively.
llvm-svn: 127486
2011-03-11 20:31:17 +00:00
Jim Grosbach
431682981d
ARM VREV64df and VREV64qf can just be patterns. The instruction is the same
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as for VREV64d32 and VREV64q32, respectively.
llvm-svn: 127485
2011-03-11 20:18:05 +00:00
Jim Grosbach
fff6ff502b
This FIXME has been fixed.
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llvm-svn: 127483
2011-03-11 20:07:37 +00:00
Jim Grosbach
2ecded3a94
Properly pseudo-ize ARM MVNCCi.
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llvm-svn: 127482
2011-03-11 19:55:55 +00:00
Jim Grosbach
39804c0b44
Fix MOVCCi32imm to be have ARM-mode Requires and a proper size (8 bytes, was 4).
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llvm-svn: 127469
2011-03-11 18:00:42 +00:00
Jim Grosbach
ed45ac390c
Properly pseudo-ize ARM MOVCCi and MOVCCi16.
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llvm-svn: 127442
2011-03-11 01:09:28 +00:00
Jim Grosbach
1986d9ac8f
Properly pseudo-ize MOVCCr and MOVCCs.
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llvm-svn: 127434
2011-03-10 23:56:09 +00:00
Jim Grosbach
5891b1323a
DMB can just be a pat referencing MCR.
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llvm-svn: 127423
2011-03-10 19:27:17 +00:00
Jim Grosbach
4b74ef6ca9
Reorganize a bit. No functional change, just moving patterns up.
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llvm-svn: 127422
2011-03-10 19:21:08 +00:00
Jim Grosbach
db549a7f6c
Pseudo-instructions are codegenonly by definition.
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llvm-svn: 127420
2011-03-10 19:06:39 +00:00
Johnny Chen
6bf5d7a170
LLVM combines the offset mode of A8.6.199 A1 & A2 into STRBT.
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The insufficient encoding information of the combined instruction confuses the decoder wrt
UQADD16. Add extra logic to recover from that.
Fixed an assert reported by Sean Callanan
llvm-svn: 127354
2011-03-09 20:01:14 +00:00
Bill Wendling
68934338ab
* Correct encoding for VSRI.
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* Add tests for VSRI and VSLI.
llvm-svn: 127297
2011-03-09 00:33:17 +00:00
Bill Wendling
b790c462c0
Correct the encoding for VRSRA and VSRA instructions.
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llvm-svn: 127294
2011-03-09 00:00:35 +00:00
Bill Wendling
ab9f04b6d8
* Fix VRSHR and VSHR to have the correct encoding for the immediate.
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* Update the NEON shift instruction test to expect what 'as' produces.
llvm-svn: 127293
2011-03-08 23:48:09 +00:00
Bob Wilson
f8c4d1ded9
Fix a compiler crash where a Glue value had multiple uses. Radar 9049552.
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llvm-svn: 127198
2011-03-08 01:17:20 +00:00
Bob Wilson
94403e6221
Fix comment typos.
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llvm-svn: 127197
2011-03-08 01:17:16 +00:00
Bill Wendling
958e854f40
Rename the narrow shift right immediate operands to "shr_imm*" operands. Also
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expand the testing of the narrowing shift right instructions.
No functionality change.
llvm-svn: 127193
2011-03-07 23:38:41 +00:00
Cameron Zwarich
a1920d7f51
Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.
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llvm-svn: 127175
2011-03-07 21:56:36 +00:00
Anton Korobeynikov
8c7010e832
ARM assembler stuff is crazy: for .setfp positive values of offset corresponds to "add" instruction, not to "sub" as in .pad case
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llvm-svn: 127106
2011-03-05 18:44:00 +00:00
Anton Korobeynikov
f15e269356
In Thumb1 mode the constant might be materialized via the load from constpool. Emit unwinding information in case when this load from constpool is used to change the stack pointer in the prologue.
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llvm-svn: 127105
2011-03-05 18:43:55 +00:00
Anton Korobeynikov
d8873d31a8
Implement frame unwinding information emission for Thumb1. Not finished yet because there is no way given the constpool index to examine the actual entry: the reason is clones inserted by constant island pass, which are not tracked at all! The only connection is done during asmprinting time via magic label names which is really gross and needs to be eventually fixed.
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llvm-svn: 127104
2011-03-05 18:43:50 +00:00
Anton Korobeynikov
d4828b54ec
Add unwind information emission for thumb stuff
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llvm-svn: 127103
2011-03-05 18:43:43 +00:00
Anton Korobeynikov
7ba97c2831
Handle MI flags inside Thumb2SizeReduction pass.
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llvm-svn: 127102
2011-03-05 18:43:38 +00:00
Anton Korobeynikov
917ca94111
Preliminary support for ARM frame save directives emission via MI flags.
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This is just very first approximation how the stuff should be done
(e.g. ARM-only for now). More to follow.
llvm-svn: 127101
2011-03-05 18:43:32 +00:00
Anton Korobeynikov
62e48532b9
Some first rudimentary support for ARM EHABI: print exception table in "text mode".
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llvm-svn: 127099
2011-03-05 18:43:15 +00:00
Bob Wilson
1497601a7b
Remove unused conditional negate operations.
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llvm-svn: 127090
2011-03-05 16:54:31 +00:00
Devang Patel
23ee9fdba3
Disable ARMGlobalMerge on darwin. The debugger is not yet able to extract individual variable's info from merged global.
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llvm-svn: 127019
2011-03-04 19:11:05 +00:00
Bob Wilson
c48ba54186
PR8053: Fix encoding of S bit in some ARM instructions.
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Patch by Zonr Chang!
llvm-svn: 126967
2011-03-03 23:07:15 +00:00
Bob Wilson
72ccdfe148
Add a readme entry for the redundant movw issue for pr9370.
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llvm-svn: 126930
2011-03-03 06:39:09 +00:00
Bob Wilson
42f80596ca
pr9367: Add missing predicated BLX instructions.
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Patch by Jyun-Yan You, with some minor adjustments and a testcase from me.
llvm-svn: 126915
2011-03-03 01:41:01 +00:00
Kevin Enderby
58cc960338
Fixes an assertion failure while disassembling ARM rsbs reg/reg form.
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Patch by Ted Kremenek!
llvm-svn: 126895
2011-03-02 23:08:33 +00:00