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1976 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
3bc582fa67 Fixed stack frame addressing bug 
llvm-svn: 41160
 2007-08-18 02:19:09 +00:00
Bruno Cardoso Lopes
15cbbbb56f support for Schedule included on Mips.td 
llvm-svn: 41159
 2007-08-18 02:18:07 +00:00
Bruno Cardoso Lopes
e2909db54c Removed LowerRETURADDR, fixed small bug into LowerRET, LowerGlobalAddress 
fixed to generate instructions (add, lui) glued!

llvm-svn: 41158
 2007-08-18 02:16:30 +00:00
Bruno Cardoso Lopes
d13e0b33d1 Couple of small changes. Delay Slot handle header declared. 
Newline added after macros at function init on generated asm!

llvm-svn: 41157
 2007-08-18 02:05:24 +00:00
Bruno Cardoso Lopes
1ad2687157 Added InstrItinClass support for instruction formats 
llvm-svn: 41156
 2007-08-18 02:01:28 +00:00
Bruno Cardoso Lopes
0dce1a316c Branch Analysis and InsertNoop inserted into header files 
llvm-svn: 41155
 2007-08-18 01:59:45 +00:00
Bruno Cardoso Lopes
ae01dc5e74 createMipsDelaySlotFillerPass added to mips codegen runtime 
llvm-svn: 41154
 2007-08-18 01:58:15 +00:00
Bruno Cardoso Lopes
7bca87bebd Added Branch Analysis support 
Added InsertNoop support

llvm-svn: 41153
 2007-08-18 01:56:48 +00:00
Bruno Cardoso Lopes
c7eaab9c92 LowerRETURNADDR removed since it was wrong and does not have utility yet! 
MipsAdd opcode added

llvm-svn: 41152
 2007-08-18 01:54:09 +00:00
Bruno Cardoso Lopes
d97285f98a InstrItineraryData support on added. 
Added Mips3 ISA feature (needed when supporting R4000 machines)

llvm-svn: 41151
 2007-08-18 01:52:27 +00:00
Bruno Cardoso Lopes
bc755b9969 A Pass to insert Nops on intructions with DelaySlot 
llvm-svn: 41150
 2007-08-18 01:50:47 +00:00
Bruno Cardoso Lopes
d67580757e Mips generic fallback instruction schedule support! 
llvm-svn: 41149
 2007-08-18 01:46:44 +00:00
Dan Gohman
352de5aeb9 More explicit keywords. 
llvm-svn: 40757
 2007-08-02 21:21:54 +00:00
Duncan Sands
e8bb2c6d32 Support for trampolines, except for X86 codegen which is 
still under discussion.

llvm-svn: 40549
 2007-07-27 12:58:54 +00:00
Dan Gohman
0fc4e0cf47 Don't ignore the return value of AsmPrinter::doInitialization and 
AsmPrinter::doFinalization.

llvm-svn: 40487
 2007-07-25 19:33:14 +00:00
Evan Cheng
53cb03b583 No more noResults. 
llvm-svn: 40132
 2007-07-21 00:34:19 +00:00
Evan Cheng
8312ed6f77 Change instruction description to split OperandList into OutOperandList and 
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033
 2007-07-19 01:14:50 +00:00
Bruno Cardoso Lopes
27f5beafb2 Added support for Mips specific GAS directives 
Fixed print immediate 
Fixed Identation on MipsISelDAGToDAG.cpp

llvm-svn: 39764
 2007-07-11 23:24:41 +00:00
Bruno Cardoso Lopes
e21704313d Added support for framepointer 
Prologue/Epilogue support fp,ra save/restore and use the stack frame the right
way!

llvm-svn: 39763
 2007-07-11 23:21:31 +00:00
Bruno Cardoso Lopes
0ba66ea1dc Now that stack is represented the right way, LOA starts at 0 
llvm-svn: 39761
 2007-07-11 23:17:41 +00:00
Bruno Cardoso Lopes
be14b3c16c Fixed AddLiveOut issues 
FI's created the write way to represent Mips stack

llvm-svn: 39760
 2007-07-11 23:16:16 +00:00
Bruno Cardoso Lopes
bc1b534410 Removed unused immediate PatLeaf, fixed lui instruction 
llvm-svn: 39759
 2007-07-11 22:47:02 +00:00
Bruno Cardoso Lopes
a851ed6989 Added MipsMachineFunction class, to hold Mips dinamic stack info when inserting Prologue/Epilog 
llvm-svn: 39758
 2007-07-11 22:44:21 +00:00
Lauro Ramos Venancio
18fc770fd0 Assert when TLS is not implemented. 
llvm-svn: 39737
 2007-07-11 17:19:51 +00:00
Chris Lattner
4810c53b05 The various "getModuleMatchQuality" implementations should return 
zero if they see a target triple they don't understand.

llvm-svn: 38463
 2007-07-09 17:25:29 +00:00
Bruno Cardoso Lopes
709699b8d3 Initial Mips support, here we go! =) 
- Modifications from the last patch included
  (issues pointed by Evan Cheng are now fixed).
- Added more MipsI instructions.
- Added more patterns to match branch instructions.

llvm-svn: 37461
 2007-06-06 07:42:06 +00:00