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Commit Graph

9 Commits

Author SHA1 Message Date
Misha Brukman
ee88ddfc38 Added instruction format class 3.15 and floating-point compare instructions.
llvm-svn: 6594
2003-06-04 02:26:14 +00:00
Misha Brukman
4c382415f6 Store instructions are different from other Format 3.1/3.2 instructions in that
they prefer the destination register to be last. Thus, two new classes were made
for them that accomodate for having this layout of operands (F3_1rd, F3_2rd).

llvm-svn: 6564
2003-06-03 03:20:14 +00:00
Misha Brukman
2de19586d6 * Removed unused classes: the rd field is always mentioned as the last reg.
* Added new classes which start building from rs1, adding rs2, and then rd.
* Fixed order of operands in classes 3.11, 3.12, 3.16, and 3.17 .
* Fixed comments to reflect Real Life (tm).
* Removed "don't care" commented out assignments and dead classes (#if 0).

llvm-svn: 6560
2003-06-03 01:11:58 +00:00
Misha Brukman
f343fb82d0 Added MOVR (move int reg on register condition), aka comparison with zero.
None of these instructions are actually used in the Sparc backend, so no changes
were required in the instruction selector.

llvm-svn: 6549
2003-06-02 21:16:54 +00:00
Misha Brukman
32fae9b78a The 'rd' register is consistently mentioned last in instruction definitions.
Created new classes from which instructions inherit their ordering of fields.

llvm-svn: 6461
2003-05-31 06:25:19 +00:00
Misha Brukman
0fae161230 The actual order of parameters in a 2-reg-immediate assembly instructions is
"rs1, imm, rd": most importantly, rd goes last.

llvm-svn: 6456
2003-05-31 04:22:26 +00:00
Misha Brukman
9c38927f33 Because the format of the shift instructions is `shift r, shcnt, r', the
instructions of format 3.12 and 3.13 cannot inherit from F3rdrs1, because that
implies that the two registers are the first two parameters to the instruction.

Thus I made the instructions inherit from F3rd again, and manually added an rs1
field AFTER the shcnt field in the instruction, which maps to the appropriate
place in the instruction.

The other changes are just elimination of unnecessary spaces.

llvm-svn: 6437
2003-05-30 18:06:10 +00:00
Brian Gaeke
240b6d81b8 Makefile: Make SparcV9CodeEmitter.inc depend on SparcV9_F*.td as well.
SparcV9_F3.td: F3_12 and F3_13 instructions have rd and rs1 fields. Also,
 their fields were totally screwed up. This seems to fix the problem.

llvm-svn: 6429
2003-05-30 08:02:14 +00:00
Misha Brukman
d0b1d8fa42 * Broke up SparcV9.td into separate files as it was getting unmanageable
* Added some Format 4 classes, but not instructions
* Added notes on missing sections with FIXMEs
* Added RDCCR instr

llvm-svn: 6388
2003-05-29 03:31:43 +00:00