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Commit Graph

211753 Commits

Author SHA1 Message Date
Fangrui Song
ee9cc55e48 [test] Improve SanitizerCoverage tests on !associated and comdat 2021-02-24 16:51:41 -08:00
Jonas Devlieghere
f7b7e8bc87 [llvm] Check availability for os_signpost
Add availability checks to the os_signpost code so this can be used with
an older deployment target.

Differential revision: https://reviews.llvm.org/D97410
2021-02-24 16:27:31 -08:00
Craig Topper
16955deca8 [RISCV] Teach VSETVLI inserter to use VSETIVLI when possible.
We always create the VL operand using a register, but if we can
determine that it came from an ADDI X0, imm with a sufficiently
small immediate, we can use VSETIVLI.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D97332
2021-02-24 16:07:33 -08:00
Craig Topper
45b51bfba7 [RISCV] Use a ComplexPattern for zexti32 to match sexti32.
We just started using a ComplexPattern for sexti32. This updates
zexti32 to match.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D97231
2021-02-24 16:06:29 -08:00
Stefan Agner
53b1283520 [MC][ARM] make Thumb function also if type attribute is set
Make sure to set the bottom bit of the symbol even when the type
attribute of a label is set after the label.

GNU as sets the thumb state according to the thumb state of the label.
If a .type directive is placed after the label, set the symbol's thumb
state according to the thumb state of the .type directive. This matches
GNU as in most cases.

From: Stefan Agner <stefan@agner.ch>

This fixes:
https://bugs.llvm.org/show_bug.cgi?id=44860
https://github.com/ClangBuiltLinux/linux/issues/866

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D74927
2021-02-24 14:08:56 -08:00
Petr Hosek
17dfbfc9e3 Revert "[Profile] Include a few asserts in coverage mapping test"
This reverts commit 80f329bcd0281c11062879025761d0657167fe8b.
2021-02-24 14:01:42 -08:00
Sanjay Patel
5df3040303 [InstCombine] fold fdiv with powi divisor (PR49147)
This extends b40fde062c for the especially non-standard
powi pattern. We want to avoid being completely wrong
on the negation-of-int-min corner case, so I'm adding
an extra FMF check for 'ninf' assuming that gives us
the flexibility to handle that possibility.
https://llvm.org/PR49147
2021-02-24 16:44:36 -05:00
Sanjay Patel
47a1678251 [InstCombine] add helper for x/pow(); NFC
We at least want to add powi to this list, so
split it off into a switch to reduce code duplication.
2021-02-24 16:44:36 -05:00
Petr Hosek
eceb39715e [Profile] Include a few asserts in coverage mapping test
These should catch any accidental use of the compilation directory.

Differential Revision: https://reviews.llvm.org/D97402
2021-02-24 13:42:45 -08:00
Duncan P. N. Exon Smith
5c2785ddb8 Transforms: Clone distinct nodes in metadata mapper unless RF_ReuseAndMutateDistinctMDs
This is a follow up to 22a52dfddcefad4f275eb8ad1cc0e200074c2d8a and a
revert of df763188c9a1ecb1e7e5c4d4ea53a99fbb755903.

With this change, we only skip cloning distinct nodes in
MDNodeMapper::mapDistinct if RF_ReuseAndMutateDistinctMDs, dropping the
no-longer-needed local helper `cloneOrBuildODR()`.  Skipping cloning in
other cases is unsound and breaks CloneModule, which is why the textual
IR for PR48841 didn't pass previously. This commit adds the test as:
Transforms/ThinLTOBitcodeWriter/cfi-debug-info-cloned-type-references-global-value.ll

Cloning less often exposed a hole in subprogram cloning in
CloneFunctionInto thanks to df763188c9a1ecb1e7e5c4d4ea53a99fbb755903's
test ThinLTO/X86/Inputs/dicompositetype-unique-alias.ll. If a function
has a subprogram attachment whose scope is a DICompositeType that
shouldn't be cloned, but it has no internal debug info pointing at that
type, that composite type was being cloned. This commit plugs that hole,
calling DebugInfoFinder::processSubprogram from CloneFunctionInto.

As hinted at in 22a52dfddcefad4f275eb8ad1cc0e200074c2d8a's commit
message, I think we need to formalize ownership of metadata a bit more
so that ValueMapper/CloneFunctionInto (and similar functions) can deal
with cloning (or not) metadata in a more generic, less fragile way.

This fixes PR48841.

Differential Revision: https://reviews.llvm.org/D96734
2021-02-24 12:57:52 -08:00
Duncan P. N. Exon Smith
841602d8d7 IR: Rename Metadata::ImplicitCode to SubclassData1, NFC
Metadata::ImplicitCode is a bit shaved off of Metadata::Storage,
currently only in use by the subclass DILocation. However, the bit isn't
reserved for that purpose. Rename it `SubclassData1` to make it clear
that it has nothing to do with Metadata itself (and other subclasses are
free to use it).

As a drive-by, remove an old TODO about exposing bits to subclasses
(looks like that has mostly been done).

No functionality change here.

Differential Revision: https://reviews.llvm.org/D96740
2021-02-24 12:56:26 -08:00
Philip Reames
1bf8743dc5 [tests] precommit tests for D97219 2021-02-24 12:44:12 -08:00
Michael Liao
934464db85 [amdgpu] Atomic should be source of divergence.
Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D97392
2021-02-24 15:27:47 -05:00
Sanjay Patel
673d8e5c18 [InstCombine] add tests for fdiv+powi; NFC 2021-02-24 15:08:00 -05:00
Matt Arsenault
bc3468840a AMDGPU: Remove special case in shouldCoalesce
Unaligned registers are now constrained with classes, rather than
specially reserving a subset of the whole class.
2021-02-24 14:49:44 -05:00
Matt Arsenault
f1ba6f4d9b AMDGPU: Add even aligned VGPR/AGPR register classes
gfx90a operations require even aligned registers, but this was
previously achieved by reserving registers inside the full class.

Ideally this would be captured in the static instruction definitions
for the operands, and we would have different instructions per
subtarget. The hackiest part of this is we need to manually reassign
AGPR register classes after instruction selection (we get away without
this for VGPRs since those types are actually registered for legal
types).
2021-02-24 14:49:37 -05:00
Fangrui Song
f1e68092e6 [llvm-objcopy] If input=output, preserve umask bits, otherwise drop S_ISUID/S_ISGID bits
This makes the behavior similar to cp

```
chmod u+s,g+s,o+x a
sudo llvm-strip a -o b
// With this patch, b drops set-user-ID and set-group-ID bits.
// sudo cp a b => b does not have set-user-ID or set-group-ID bits.
```

This also changes the behavior for the following case:

```
chmod u+s,g+s,o+x a
llvm-strip a
// a preserves set-user-ID and set-group-ID bits.
// This matches binutils<2.36 and probably >=2.37.  2.36 and 2.36.1 have some compatibility issues.
```

Differential Revision: https://reviews.llvm.org/D97253
2021-02-24 11:10:09 -08:00
James Y Knight
1035ca46f9 Remove a workaround for MSVC 2013, now that MSVC 2017 is the minimum.
In MSVC 2013, 'alignas(integer-template-arg)' didn't compile; verified
on godbolt that this now works properly.
2021-02-24 13:56:49 -05:00
Jessica Paquette
3698409c51 [AArch64][GlobalISel] Fix manual selection for v4s16 and v8s8 G_DUP
The manual G_DUP selection code would produce DUPv16i8 for v8s8s and DUPv8i16
for v4s16.

This adds the missing cases to the manual selection code, and makes it return
false when there is an unexpected size.

Update select-dup.mir to reflect the change.

Differential Revision: https://reviews.llvm.org/D97240
2021-02-24 10:23:06 -08:00
Craig Topper
a68e6317f3 [RISCV] Support fixed vector extract element. Use VL=1 for scalable vector extract element.
I've changed to use VL=1 for slidedown and shifts to avoid extra
element processing that we don't need.

The i64 fixed vector handling on i32 isn't great if the vector type
isn't legal due to an ordering issue in type legalization. If the
vector type isn't legal, we fall back to default legalization
which will bitcast the vector to vXi32 and use two independent extracts.
Doing better will require handling several different cases by
manually inserting insert_subvector/extract_subvector to adjust the type
to a legal vector before emitting custom nodes.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D97319
2021-02-24 10:17:00 -08:00
Joel E. Denny
eaa132dc46 [lit] Add --ignore-fail
For some build configurations, `check-all` calls lit multiple times to
run multiple lit test suites.  Most recently, I've found this to be
true when configuring openmp as part of `LLVM_ENABLE_RUNTIMES`, but
this is not the first time.

If one test suite fails, none of the remaining test suites run, so you
cannot determine if your patch has broken them.  It can then be
frustrating to try to determine which `check-` targets will run the
remaining tests without getting stuck on the failing tests.

When such cases arise, it is probably best to adjust the cmake
configuration for `check-all` to run all test suites as part of one
lit invocation.  Because that fix will likely not be implemented and
land immediately, this patch introduces `--ignore-fail` to serve as a
workaround for developers trying to see test results until it does
land:

```
$ LIT_OPTS=--ignore-fail ninja check-all
```

One problem with `--ignore-fail` is that it makes it challenging to
detect test failures in a script, perhaps in CI.  This problem should
serve as motivation to actually fix the cmake configuration instead of
continuing to use `--ignore-fail` indefinitely.

Reviewed By: jhenderson, thopre

Differential Revision: https://reviews.llvm.org/D96371
2021-02-24 13:10:27 -05:00
Craig Topper
93c5f95d18 [LegalizeIntegerTypes] Further improve ExpandIntRes_SADDSUBO for targets where SADDO/SSUBO aren't supported.
Rather than converting 3 signbits to bools and comparing them,
we can do bitwise logic on the whole vector and convert the
resulting sign bit to a bool at the end.

This is still a different algorithm than what we do in LegalizeDAG
through expandSADDOSSUBO. That algorithm needs to know that the
RHS of SSUBO is > 0, but that's costly when the type is split.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D97325
2021-02-24 10:05:38 -08:00
Simon Pilgrim
bb3d1c71a7 Revert rGd65ddca83ff85c7345fe9a0f5a15750f01e38420 - "[ValueTracking] ComputeKnownBits - minimum leading/trailing zero bits in LSHR/SHL (PR44526)"
This is causing sanitizer test failures that I haven't been able to fix yet.
2021-02-24 18:03:17 +00:00
Nick Desaulniers
2cf4f5f7af [MC][ARM] add .w suffixes for BL (T1) and DBG
F1.2 Standard assembler syntax fields
describes .w and .n suffixes for wide and narrow encodings.

arch/arm/probes/kprobes/test-thumb.c tests installing kprobes for
certain instructions using inline asm.  There's a few instructions we
fail to assemble due to missing .w t2InstAliases.

Adds .w suffixes for:
* bl  (F5.1.25 BL, BLX (immediate) T1)
* dbg (F5.1.42 DBG T1)

Reviewed By: DavidSpickett

Differential Revision: https://reviews.llvm.org/D97236
2021-02-24 09:58:08 -08:00
Amara Emerson
9d81ca43d2 [AArch64] Do not fold SP adjustments into pre-increment addr modes if it overflows the redzone.
Instead of outright disabling this completely with the noredzone attribute,
we only avoid doing the optimization if there are memory operations between
the adjustment and the load/store that the adjustment would be folded into.
This avoids the case of something like a stack cookie being corrupted if an
exception happens before the pre-increment to the SP occurs.

This also prevents the folding happening if we have a redzone, but the offset
being folded is above the redzone amount (128 bytes in this case).

rdar://73269336

Differential Revision: https://reviews.llvm.org/D95179
2021-02-24 09:55:48 -08:00
Philip Reames
605f2ea52d [tests] precommit tests for an upcoming AA improvement 2021-02-24 09:51:00 -08:00
Philip Reames
7f1a17b009 Revert "[tests] Mark an autogened test as such"
This reverts commit 43a569faeb332ae8b355fffc33eec1ef6e33052e.

Unhelpfully, the tool just added the header and didn't actually update any of the tests.  I didn't notice until after pushing.
2021-02-24 09:26:26 -08:00
serge-sans-paille
4458621d3d Make sure some types are indeed trivially_copyable per llvm::is_trivially_copyable
Test a few types used as llvm::SmallVector parameter. It is important to ensure
we have a consistent behavior for these types to prevent ABI issues as the one
we met in https://bugs.llvm.org/show_bug.cgi?id=39427.

Differential Revision: https://reviews.llvm.org/D96536
2021-02-24 18:24:57 +01:00
Philip Reames
01ce9f6d68 [tests] Mark an autogened test as such 2021-02-24 09:15:19 -08:00
Jay Foad
759be00627 [AMDGPU] Add a bit more gfx90a test coverage
Update the GlobalISel version of llvm.amdgcn.workitem.id.ll to mostly
match the SelctionDAG version.

Differential Revision: https://reviews.llvm.org/D97377
2021-02-24 17:08:32 +00:00
Jinsong Ji
5c4630a66a [Coverage][Unittest] Fix stringref issue
We will pass StringRef and change it in reader.
But we reuse the same Filename vector without clear it,
so in some systems, we may clobbeer previous results.

Reviewed By: phosek

Differential Revision: https://reviews.llvm.org/D97353
2021-02-24 14:59:40 +00:00
Sander de Smalen
1203ef24fe [InstructionCost] NFC: Fix up missing cases in LoopVectorize and CodeGenPrep.
This fixes the types of a few more cost variables to be of type InstructionCost.
2021-02-24 14:30:03 +00:00
Nico Weber
39f1c5eb95 Revert "[ValueTracking] computeKnownBitsFromShiftOperator - remove non-zero shift amount handling."
This reverts commit d37400168ce2f1f9ccc91847431f5b8c020a7d67.
Breaks Analysis/./AnalysisTests/ComputeKnownBitsTest.KnownNonZeroShift
2021-02-24 09:06:12 -05:00
Simon Pilgrim
b83d98e3a8 [ValueTracking] computeKnownBitsFromShiftOperator - remove non-zero shift amount handling.
This no longer affects any tests after the improvements to the KnownBits shift helpers.
2021-02-24 13:49:13 +00:00
Jay Foad
68e88416c9 [AMDGPU] Add more PAL metadata register names
Add all the registers that are currently used by
LLPC: https://github.com/GPUOpen-Drivers/llpc

This only affects disassembly of PAL metadata generated by LLPC and
similar frontends.

Differential Revision: https://reviews.llvm.org/D95619
2021-02-24 13:37:05 +00:00
Jay Foad
7e3ac796de [AMDGPU] Update s_sendmsg messages
Update the list of s_sendmsg messages known to the assembler and
disassembler and validate the ones that were added or removed in gfx9
and gfx10.

Differential Revision: https://reviews.llvm.org/D97295
2021-02-24 13:07:00 +00:00
Simon Pilgrim
0bfddb64c3 [ValueTracking] ComputeKnownBits - minimum leading/trailing zero bits in LSHR/SHL (PR44526)
Followup to D72573 - as detailed in https://blog.regehr.org/archives/1709 we don't make use of the known leading/trailing zeros for shifted values in cases where we don't know the shift amount value.

Stop ValueTracking returning zero for poison shift patterns and use the KnownBits shift helpers directly.

Extend KnownBits::shl to combine all possible shifted combinations if both min/max shift amount values are in range.

Differential Revision: https://reviews.llvm.org/D90479
2021-02-24 12:15:45 +00:00
Pierre Gousseau
1ae9bf0388 [asan] Avoid putting globals in a comdat section when targetting elf.
Putting globals in a comdat for dead-stripping changes the semantic and
can potentially cause false negative odr violations at link time.
If odr indicators are used, we keep the comdat sections, as link time
odr violations will be dectected for the odr indicator symbols.

This fixes PR 47925
2021-02-24 12:01:56 +00:00
Simon Pilgrim
4081766ef3 [Utils] collectBitParts - add truncate() handling 2021-02-24 11:48:34 +00:00
Lang Hames
4e02a88925 [docs][JITLink] Remove the JITLink doc for now.
I'll reinstate and continue investigation tomorrow.
2021-02-24 22:32:18 +11:00
Lang Hames
9a46912f53 [docs][JITLink] Yet more experiments to try to understand sphinx error. 2021-02-24 22:22:48 +11:00
Lang Hames
1022a61830 [docs][JITLink] More experiments to try to understand sphinx error. 2021-02-24 22:22:47 +11:00
Simon Pilgrim
8537b194aa [DAG] Add basic mul-with-overflow constant folding support
As noticed on D97160
2021-02-24 11:09:02 +00:00
Lang Hames
296cd8fcdb [docs][JITLink] Make `ObjectLinkingLayer` not a paragraph start.
More experiments as I try to placate sphinx.
2021-02-24 22:04:14 +11:00
Lang Hames
972cb5e278 [docs][JITLink] Return to `` for inline literals.
Also awkwardly reformat text to test whether the error is occurring
on the line with the '::', or the previous one.
2021-02-24 21:55:49 +11:00
Lang Hames
bceb5d6608 [docs][JITLink] Try explicit literal blocks for monospace list elements. 2021-02-24 21:50:27 +11:00
Lang Hames
eeb1165ed0 [docs][JITLink] More attempted fixes for formatting issues in the JITLink doc.
Try using the literal domain for `ObjectLinkingLayer::Plugin` and literal
blocks for multi-line method names.
2021-02-24 21:41:27 +11:00
Florian Hahn
9dca79de19 Recommit "[LV] Allow tryToCreateWidenRecipe to return a VPValue, use for blends."
This reverts the revert commit 437f0bbcd509d0ed71b91ec1f86f48c2f4aae980.

It adds a new toVPRecipeResult, which forces VPRecipeOrVPValueTy to be
constructed with a VPRecipeBase *. This should address ambiguous
constructor issues for recipe sub-types that also inherit from VPValue.
2021-02-24 10:36:02 +00:00
Lang Hames
009afd2bc6 [docs][JITLink] Sphinx does not like '::' in monotype. Try using a
cpp domain expr instead.
2021-02-24 21:23:10 +11:00
Lang Hames
e6ec15b603 [docs][JITLink] Add a JITLink design and API document. 2021-02-24 21:04:35 +11:00